X28C010KM-25 Datasheet, PDF (13/20 Pages) Intersil Corporation – Protects data against system level inadvertent writes

WE Controlled Write Cycle
Address
CE
t_AS
t_CS
X28C010, X28HT010
t_WC
t_AH
t_CH
OE
t_OES
t_OEH
t_WP
WE
t_DV
t_WPH
Data In
Data Valid
t_DS
t_DH
Data Out
HIGH Z
NOTE:
5. t_WC is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum time the device
requires to complete internal write operation.
CE Controlled Write Cycle
Address
CE
t_AS
t_OES
t_AH
t_CW
t_WC
t_WPH
OE
WE
Data In
Data Out
t_CS
t_DV
t_OEH
t_CH
Data Valid
t_DS
t_DH
HIGH Z
13
FN8105.1
February 12, 2007