ISL70001SEH Datasheet, PDF (14/17 Pages) Intersil Corporation – Rad Hard and SEE Hard 6A Synchronous Buck Regulator

ISL70001SEH
PCB Design
PCB design is critical to high-frequency switching regulator
performance. Careful component placement and trace routing
are necessary to reduce voltage spikes and minimize
undesirable voltage drops. Selection of a suitable thermal
interface material is also required for optimum heat dissipation
and to provide lead strain relief. See Table 1 on page 16 for
layout x-y coordinates.
PCB Plane Allocation
Four layers of 2-ounce copper are recommended. Layer 2 should
be a dedicated ground plane with all critical component ground
connections made with vias to this layer. Layer 3 should be a
dedicated power plane split between the input and output power
rails. Layers 1 and 4 should be used primarily for signals but can
also provide additional power and ground islands, as required.
PCB Component Placement
Components should be placed as close as possible to the IC to
minimize stray inductance and resistance. Prioritize the
placement of bypass capacitors on the pins of the IC in the order
shown: REF, SS, AVDD, DVDD, PVINx (high frequency capacitors),
EN, PGOOD, PVINx (bulk capacitors).
Locate the output voltage resistive divider as close as possible to
the FB pin of the IC. The top leg of the divider should connect
directly to the POL (Point of Load), and the bottom leg of the
divider should connect directly to AGND. The junction of the
resistive divider should connect directly to the FB pin.
Locate a Schottky clamp diode as close as possible to the LXx
and PGNDx pins of the IC. A small series R-C snubber connected
from the LXx pins to the PGNDx pins may be used to damp high
frequency ringing on the LXx pins, if desired, see Figure 11.
ERROR
AMPLIFIER
-
+ ^VREF
LXx
L_OUT
3A
R_S
C_S
PGNDx
FB
REF
C_REF
C_OUT
V_OUT
R_{T CC}
R_B
FIGURE 11. SCHOTTKY DIODE AND R-C SNUBBER
PCB Layout
Use a small island of copper to connect the LXx pins of the IC to
the output inductor on Layers 1 and 4. To minimize capacitive
coupling to the power and ground planes, void the copper on
Layers 2 and 3 adjacent to the island. Place most of the island of
Layer 4 to minimize the amount of copper that must be voided
from the ground plane (Layer 2).
Keep all other signal traces as short as possible.
For an example layout, see AN1518.
Thermal Management
For optimum thermal performance, place a pattern of vias on the
top layer of the PCB directly underneath the IC. Connect the vias
to the ground plane on Layer 2, which serves as a heat sink. To
ensure good thermal contact, thermal interface material such as
a Sil-Pad or thermally conductive epoxy should be used to fill the
gap between the vias and the bottom of the IC.
Lead Strain Relief
For strain relief, a Sil-Pad or a thin layer of thermally conductive
epoxy can be used to raise the bottom of the IC from the PCB
surface so that a slight bend can be added to the leads of the IC.
14
FN7956.0
November 30, 2011