ISL6753_06 Datasheet, PDF (14/15 Pages) Intersil Corporation – ZVS Full-Bridge PWM Controller

ISL6753
The second power transfer period commences when switch
LL closes. With switches UR and LL on, the primary and
secondary currents flow as indicated below.
VIN+
UL
UR
D1
L_L
VOUT+
RTN
LL
LR
D2
VIN-
FIGURE 14. UR - LL POWER TRANSFER
The UR - LL power transfer period terminates when switch
LL turns off as determined by the PWM. The current flowing
in the primary must find an alternate path. The current flows
into the parasitic switch capacitance which charges the node
to VIN and then forward biases the body diode of upper
switch UL. As before, the output inductor current assists in
this transition. The primary leakage inductance, L_L,
maintains the current, which now circulates around the path
of switch UR, the transformer primary, and switch UL. When
switch LL opens, the output inductor current free-wheels
predominantly through diode D1. Diode D2 may actually
conduct very little or none of the free-wheeling current,
depending on circuit parasitics. This condition persists
through the remainder of the half-cycle.
VIN+
UL
I_P
UR
L_L
D1
I_S
LL
LR
D2
VIN-
FIGURE 15. UR - UL FREE-WHEELING PERIOD
VOUT+
RTN
When the upper switches toggle, the primary current that
was flowing through UR must find an alternate path. It
charges/discharges the parasitic capacitance of switches UR
and LR until the body diode of LR is forward biased. If
RESDEL is set properly, switch LR will be turned on at this
time.
VIN+
UL
I_P
LL
UR
L_L
LR
D1
I_S
D2
VOUT+
RTN
VIN-
FIGURE 16. UPPER SWITCH TOGGLE AND RESONANT
TRANSITION
The first power transfer period commences when switch LR
closes and the cycle repeats. The ZVS transition requires
that the leakage inductance has sufficient energy stored to
fully charge the parasitic capacitances. Since the energy
stored is proportional to the square of the current (1/2 L_LI_P2),
the ZVS resonant transition is load dependent. If the leakage
inductance is not able to store sufficient energy for ZVS, a
discrete inductor may be added in series with the
transformer primary.
Fault Conditions
A fault condition occurs if VREF or VDD fall below their
undervoltage lockout (UVLO) thresholds or if the thermal
protection is triggered. When a fault is detected, the soft-
start capacitor is quickly discharged, and the outputs are
disabled low. When the fault condition clears and the soft-
start voltage is below the reset threshold, a soft-start cycle
begins.
An overcurrent condition is not considered a fault and does
not result in a shutdown.
Thermal Protection
Internal die over temperature protection is provided. An
integrated temperature sensor protects the device should
the junction temperature exceed 140°C. There is
approximately 15°C of hysteresis.
Ground Plane Requirements
Careful layout is essential for satisfactory operation of the
device. A good ground plane must be employed. VDD and
VREF should be bypassed directly to GND with good high
frequency capacitance.
References
[1] Ridley, R., “A New Continuous-Time Model for Current
Mode Control”, IEEE Transactions on Power
Electronics, Vol. 6, No. 2, April 1991.
14
FN9182.2
April 4, 2006