ISL6742B Datasheet, PDF (14/20 Pages) Intersil Corporation – Fast current sense to output delay

ISL6742B
RAMP waveform is compared to the VERR voltage to determine
duty cycle. The selection of the RC components depends upon
the desired input voltage operating range and the frequency of
the oscillator. In typical applications, the RC components are
selected so that the ramp amplitude reaches 1V at minimum
input voltage within the duration of one half-cycle.
VIN
R₃
C₇
1
16
2
15
3
14
4 ISL6742B 13
5
12
6 RAMP
11
7
10
8
GND 9
a small resistor in series with the timing capacitor, the oscillator
sawtooth waveform may be terminated prematurely.
The injected pulse width should be narrower than the sawtooth
discharge duration.
1
16
2
15
3
14
4 CT
13
C_T
5
ISL6742B ¹²
6
11
7
10
8
GND 9
R_S
FIGURE 12. VOLTAGE FEED-FORWARD CONTROL
Referring to Figure 12, the charging time of the ramp capacitor is
expressed in Equation 8:
t
=
–R₃  C₇ 
ln


1

–
V_{-----R---V-A----IM-N----P---M---P-I--N-E---A----K----}
s
(EQ. 8)
For optimum performance, the maximum value of the capacitor
should be limited to 10nF. The DC current through the resistor
should be limited to 3mA. For example, if the oscillator frequency
is 400kHz, the minimum input voltage is 300V and a 4.7nF ramp
capacitor is selected. The value of the resistor can be determined
by rearranging Equation 8.
R₃
=
-----------------------------------–---^t----------------------------------
C₇

ln


1

–
V_{-----R--V--A--I--MN-----P-M-----PI--N--E---A----K----}
=
-----------------–---²---^.--⁵-----^---¹---⁰----^–--⁶------------------
4.7  10^–9  ln _1 – ₃----₀₁---₀--_
= 159k
(EQ. 9)
Where t is equal to the oscillator period minus the dead time. If
the dead time is short relative to the oscillator period, it can be
ignored for this calculation.
When implemented, the voltage feed-forward feature also
provides a volt-second clamp on the transformer. The maximum
duty cycle is determined by the lesser of the oscillator period or
the RAMP charge time. As the input voltage increases, the RAMP
charge time decreases, limiting the duty cycle proportionately.
If feed-forward operation is not desired, the RC network may be
connected to VREF or a buffered CT signal rather than the input
voltage. Regardless, a sawtooth waveform must be generated on
RAMP as it is required for proper PWM operation.
Implementing Synchronization
Synchronization to an external clock signal may be accomplished
in the same manner as many PWM controllers that do not have a
separate synchronization input. By injecting a short pulse across
FIGURE 13. SYNCHRONIZATION TO AN EXTERNAL CLOCK
Synchronous Rectifier Outputs and Control
The ISL6742B provides double-ended PWM outputs, OUTA and
OUTB, and Synchronous Rectifier (SR) outputs, OUTAN and
OUTBN. The SR outputs are the complements of the PWM
outputs. It should be noted that complemented outputs are used
in conjunction with the opposite PWM output, i.e., OUTA and
OUTBN are paired together and OUTB and OUTAN are paired
together.
Referring to Figure 14, the SRs alternate between being both on
during the free-wheeling portion of the cycle (OUTA/OUTB off),
and one or the other being off when OUTA or OUTB is on. If OUTA
is on, its corresponding SR must also be on, indicating that
OUTBN is the correct SR control signal. Likewise, if OUTB is on, its
corresponding SR must also be on, indicating that OUTAN is the
correct SR control signal.
CT
OUTA
OUTB
OUTAN
(SR1)
OUTBN
(SR2)
FIGURE 14. BASIC WAVEFORM TIMING
A useful feature of the ISL6742B is the ability to vary the phase
relationship between the PWM outputs (OUTA, OUTB) and their
complements (OUTAN, OUTBN) by ±300ns. This feature allows
the designer to compensate for differences in the signal
Submit Document Feedback ₁₄
FN8565.1
November 3, 2015