ISL6558 Datasheet, PDF (14/16 Pages) Intersil Corporation – Multi-Purpose Precision Multi-Phase PWM Controller With Optional Active Voltage Positioning

ISL6558
The total output ripple current can be determined from the
curves in Figure 10. They provide the total ripple current as a
function of duty cycle and number of active channels,
normalized to the parameter K_NORM at zero duty cycle.
KNORM
=
--V----O------U----T----
LxFSW
(EQ. 11)
where L is the channel inductor value.
1.0
SINGLE
0.8
CHANNEL
0.6
0.4
3 CHANNEL
0.2
4 CHANNEL
2 CHANNEL
0
0
0.1
0.2
0.3
0.4
0.5
DUTY CYCLE (V_O/V_IN)
FIGURE 10. RIPPLE CURRENT vs DUTY CYCLE
Find the intersection of the active channel curve and duty
cycle for your particular application. The resulting ripple
current multiplier from the y-axis is then multiplied by the
normalization factor, K_NORM, to determine the total output
ripple current for the given application.
DITOTAL = KNORMxKCM
(EQ. 12)
INPUT CAPACITOR SELECTION
Use a mix of input bypass capacitors to control the voltage
overshoot across the MOSFETs. Use ceramic capacitors for
the high frequency decoupling and bulk capacitors to supply
the RMS current. Small ceramic capacitors can be placed
very close to the upper MOSFET to suppress the voltage
induced in the parasitic circuit impedances.
Two important parameters to consider when selecting the
bulk input capacitor are the voltage rating and the RMS
current rating. For reliable operation, select a bulk capacitor
with voltage and current ratings above the maximum input
voltage and largest RMS current required by the circuit. The
capacitor voltage rating should be at least 1.25 times greater
than the maximum input voltage and a voltage rating of 1.5
times is a conservative guideline. The RMS current
requirement for a converter design can be approximated with
the aid of Figure 11. Follow the curve for the number of active
channels in the converter design. Next determine the duty
cycle for the converter and find the intersection of this value
and the active channel curve. Find the corresponding y-axis
value, which is the current multiplier. Multiply the total full load
output current, not the channel value, by the current multiplier
value found and the result is the RMS input current which
must be supported by the input capacitors.
0.5
SINGLE
0.4
CHANNEL
0.3
2 CHANNEL
0.2
3 CHANNEL
0.1
4 CHANNEL
0
0
0.1
0.2
0.3
0.4
0.5
DUTY CYCLE (V_O/V_IN)
FIGURE 11. CURRENT MULTIPLIER vs DUTY CYCLE
MOSFET SELECTION AND CONSIDERATIONS
The ISL6558 requires two N-Channel power MOSFETs per
active channel or more if parallel MOSFETs are employed.
These MOSFETs should be selected based upon r_DS(ON),
total gate charge, and thermal management requirements.
In high-current PWM applications, the MOSFET power
dissipation, package selection and heatsink are the
dominant design factors. The power dissipation includes two
loss components; conduction loss and switching loss. These
losses are distributed between the upper and lower
MOSFETs according to duty cycle of the converter (see the
equations below). The conduction losses are the main
component of power dissipation for the lower MOSFETs, Q2
and Q4 of Figure 1. Only the upper MOSFETs, Q1 and Q3
have significant switching losses, since the lower device turn
on and off into near zero voltage.
The following equations assume linear voltage-current
transitions and do not model power loss due to the reverse-
recovery of the lower MOSFETs body diode. The gate-
charge losses are dissipated in the HIP660x drivers and
don’t heat the MOSFETs. However, large gate-charge
increases the switching time, t_SW which increases the upper
MOSFET switching losses. Ensure that both MOSFETs are
within their maximum junction temperature at high ambient
temperature by calculating the temperature rise according to
package thermal-resistance specifications. A separate
heatsink may be necessary depending upon MOSFET
power, package type, ambient temperature and air flow.
P_UPPER
=
I_--O-----²_----×_-----r_{--D----S----(--O-----N----)---}×_-----V_{----O-----U----T-- + -}I_-O------×_-----V_{----I--N-----}×_-----t_{--S----W------}×_-----F_{----S----W---}
V_IN
2
(EQ. 13)
P_LOWER
=
I_--O-----²_----×_-----r_{--D----S----(--O-----N----)---}×_-----(_---V_{----I--N-----–----}V_{-----O----U----T----})
V_IN
(EQ. 14)
14
FN9027.12
June 21, 2005