ISL6558 Datasheet, PDF (11/16 Pages) Intersil Corporation – Multi-Purpose Precision Multi-Phase PWM Controller With Optional Active Voltage Positioning

ISL6558
See Figure 6. I_TOTAL is compared with an internally
generated overcurrent trip current, I_TRIP. The overcurrent
trip current source is trimmed to 82.5µA. If I_TOTAL exceeds
the I_TRIP level, then the controller forces all PWM outputs
into three-state. This condition results in the HIP660x gate
drivers removing drive to the MOSFETs. The VSEN voltage
will begin to fall and once it descends below the PGOOD falling
threshold, the PGOOD signal transitions low.
A delay time, equal to the soft-start interval, is entered to
allow the disturbance to clear. After the delay time, the
controller then initiates a second soft-start interval. If the
output voltage comes up and regulation is achieved,
PGOOD transitions high. If the OC trip current is exceeded
during the soft start interval, the controller will again shut
down PWM operation and three-state the drivers. The
PGOOD signal will remain low and the soft-start interval will
be allowed to expire. Another soft-start interval will be
initiated after the delay interval. If an overcurrent trip occurs
again, this same cycle repeats until the fault is removed. The
OC function is shown in Figure 7 for a hard short of the
output which is applied for only a brief moment. The
converter quickly detects the short and attempts to restart
twice before the short is removed.
Overcurrent protection reduces the regulator RMS output
current under worst case conditions to 95% of the full load
current.
SELECTING R_ISEN
The procedure for determining the value of R_ISEN is to
insure that it scales a channel’s maximum output current to
50µA. This will insure that the overcurrent trip point is
properly detected when a current limit of 165% of the
converter’s full load current is breached. The ISEN resistor
can be calculated as follows:
RISEN
=
I--F-----L-
n
x
r---D---5-S--0---_{(-µ-O---A---N----)-}
(EQ. 6)
where I_FL is the maximum output current demanded by the
load device and ‘n’ is the number of active channels.
OC TRIP LEVEL ADJUSTMENT
Setting the full load reference current, I_TOTAL, to 50µA is
recommended for most applications. The ratio between the
desired full load reference current and the internally set
overcurrent trip current is the overcurrent trip ratio, K_OC. For
those applications where an OC trip level of 1.65 times
I_TOTAL is insufficient, the full load reference current can be
scaled differently. Care must be taken in selection of certain
components once the desired OC trip ratio is determined.
KOC
=
--8---2----.-5----^µ----A----
ITOTAL
(EQ. 7)
The new overcurrent trip ratio is then used to calculate the
ISEN resistors for the new full load reference current.
RISEN
=
I--F-----L-
n
x
r---D----S-----_{(8--O--2---.-N-5---µ)---x-A--K----O------C--}
(EQ. 8)
One commonly over looked component which will change
due to the new overcurrent trip ratio is the feedback resistor,
R_FB.
RFB = ^{V-----D-----R---8-O---2---O.--5---P}_µ----xA----K----O-----C---
(EQ. 9)
Temperature effects of the MOSFET r_DS(ON) must be
reviewed when changing the overcurrent trip level.
Output Voltage Monitoring
The output voltage must be tied to the VSEN pin to provide
feedback used to create a window of operation. If the output
voltage is not the reference voltage of 0.8V, it must be
scaled externally down to this level. The VSEN voltage is
then compared with two set voltage levels which indicate an
overvoltage or undervoltage condition of the output.
Violating either of these conditions results in the PGOOD pin
output toggling low to indicate a problem with the output
voltage.
OVERVOLTAGE
The VSEN voltage is compared with an internal overvoltage
protection (OVP) reference set to 115% of the internal
reference. If the VSEN voltage exceeds the OVP reference,
the comparator simultaneously sets the OV latch and
triggers the PWM output low. The drivers turn on the lower
MOSFETs, shunting the converter output to ground. Once
the output voltage falls below the nominal output voltage, the
PWM outputs are placed in three-state. This prevents
dumping of the output capacitors back through the lower
MOSFETs. If the overvoltage conditions persist, the PWM
outputs are cycled between the two states similar to a
hysteretic regulator. The OV latch can only be reset by
cycling the VCC supply voltage to initiate a POR and begin a
soft-start interval.
UNDERVOLTAGE
The VSEN voltage is also compared to a undervoltage (UV)
reference which is set to 90% of the internal reference. If the
VSEN voltage is below the UV reference, the power good
monitor triggers PGOOD to go low. The UV comparator does
not influence converter operation.
VSEN SCALING
The output voltage, V_OUT, must be fed back to the VSEN pin
separately from the feedback components to the FB pin. If
VSEN and FB are tied together, the error amplifier will hold
the VSEN voltage at the reference level while the actual
output voltage level could be much different. This would
mask the output voltage and prevent the protection features
11
FN9027.12
June 21, 2005