ISL6341 Datasheet, PDF (14/17 Pages) Intersil Corporation – 5V or 12V Single Synchronous Buck Pulse-Width Modulation (PWM) Controller

ISL6341, ISL6341A, ISL6341B, ISL6341C
The compensation network consists of the error amplifier
(internal to the ISL6341x) and the external R₁ to R₃, C₁ to C₃
components. The goal of the compensation network is to
provide a closed loop transfer function with high 0dB crossing
frequency (F₀; typically 0.1 to 0.3 of f_SW) and adequate phase
margin (better than 45°). Phase margin is the difference
between the closed loop phase at F_0dB and 180°. The
equations that follow relate the compensation network’s poles,
zeros and gain to the components (R₁, R₂, R₃, C₁, C₂, and
C₃) in Figure 13. Use the following guidelines for locating the
poles and zeros of the compensation network:
4. Select a value for R₁ (1kΩ to 5kΩ, typically). Calculate the
value for R₂ for desired converter bandwidth (F₀). If
setting the output voltage via an offset resistor connected
to the FB pin (R_o in Figure 13), the design procedure can
be followed as presented in Equation 4.
R₂ = -_d--^V-_M----^O-_A---^S-_X---^C--_â‹---_V^â‹---^R-_I--_N--¹---_â‹-^â‹--_F-^F---_L-⁰--_C---
(EQ. 4)
5. Calculate C₁ such that F_Z1 is placed at a fraction of the F_LC,
at 0.1 to 0.75 of F_LC (to adjust, change the 0.5 factor to
desired number). The higher the quality factor of the output
filter and/or the higher the ratio F_CE/F_LC, the lower the F_Z1
frequency (to maximize phase boost at F_LC).
C₁ = -₂---_π-----_â‹---_R-----₂----_â‹--¹-₀---_.--₅-----_â‹---_F----_L---_C--
(EQ. 5)
6. Calculate C₂ such that F_P1 is placed at F_CE.
C₂
=
-------------------------^C-----¹-------------------------
2π ⋅ R₂ ⋅ C₁ ⋅ F_CE – 1
(EQ. 6)
7. Calculate R₃ such that F_Z2 is placed at F_LC. Calculate C₃
such that F_P2 is placed below f_SW (typically, 0.5 to 1.0
times f_SW). f_SW represents the switching frequency.
Change the numerical factor to reflect desired placement
of this pole. Placement of F_P2 lower in frequency helps
reduce the gain of the compensation network at high
frequency, in turn reducing the HF ripple component at
the COMP pin and minimizing resultant duty cycle jitter.
R₃
=
-------^R-----¹-------
-^f--^S---^W----
F_LC
–
1
C₃ = ₂----_π-----_â‹---_R-----₃----_â‹-¹--₀---_.--₇-----_â‹---_f--_S----_W---
(EQ. 7)
It is recommended that a mathematical model be used to
plot the loop response. Check the loop gain against the error
amplifier’s open-loop gain. Verify phase margin results and
adjust as necessary. Equations 8 and 9 describe the
frequency response of the modulator (G_MOD), feedback
compensation (G_FB) and closed-loop response (G_CL):
G_MOD(f)
=
-^d---^M-----^A----^X-----^â‹---^V----^I--^N--
V_OSC
⋅
--------------------------¹-----+-----^s----⁽--^f--⁾----^â‹---^E-----^â‹---^C-----------------------------
1 + s(f) ⋅ (E + D) ⋅ C + s²(f) ⋅ L ⋅ C
G_FB(f)
=
⋅
-----¹-----+-----^s---⁽--^f---⁾---^â‹---^R----²-----^â‹---^C---¹------ ⋅
s_---(_--f_---)_---⋅_---^R_----1_-----⋅_---(_--^C_--1--1_{---+--+---s--}^C_-(--2f_---)-)_{--⋅---(--R----1-----+-----R----3----)---⋅---C----3-------------------------------}
(
1
+
s
(f)
⋅
R₃
⋅
C₃
)
⋅
⎛
⎜
⎝
1
+
s
(
f
)
⋅
R₂
⋅
⎛
⎜
⎝
C^-C---₁^{-1----+-⋅---C-}C^---2-₂^--_{⎠⎟⎞⎠⎟⎞}
G_CL(f) = G_MOD(f) ⋅ G_FB(f)
where, s(f) = 2π ⋅ f ⋅ j
(EQ. 8)
COMPENSATION BREAK FREQUENCY EQUATIONS
F_Z1
=
--------------¹---------------
2π ⋅ ^R2 ⋅ ^C1
F_P1
=
---------------------¹----------------------
2
π
⋅
R₂
⋅
-^C----¹-----^â‹---^C----²---
C_{1 +} C₂
(EQ. 9)
F_Z2
=
-----------------------¹-------------------------
2π ⋅ (^R1 + ^R3) ⋅ ^C3
F_P2
=
--------------¹---------------
2π ⋅ ^R3 ⋅ ^C3
F_Z1F_Z2 F_P1
F_P2
MODULATOR GAIN
COMPENSATION GAIN
CLOSED LOOP GAIN
OPEN LOOP E/A GAIN
20
log
⎛
⎜
⎜
⎝
RR_{-----21--⎠⎟⎟⎞}
0
20log -^d----^M-----^A-----^X-----^â‹----V----I--N---
V_OSC
G_FB
G_CL
G_MOD
LOG
F_LC F_CE F₀
FREQUENCY
FIGURE 14. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
Figure 14 shows an asymptotic plot of the DC/DC converter’s
gain vs frequency. The actual Modulator Gain has a high gain
peak dependent on the quality factor (Q) of the output filter,
which is not shown. Using the previous guidelines should yield
a compensation gain similar to the curve plotted. The open loop
error amplifier gain bounds the compensation gain. Check the
compensation gain at F_P2 against the capabilities of the error
amplifier. The closed loop gain, G_CL, is constructed on the log-
log graph of Figure 14 by adding the modulator gain, G_MOD (in
dB), to the feedback compensation gain, G_FB (in dB). This is
equivalent to multiplying the modulator transfer function and the
compensation transfer function and then plotting the resulting
gain.
A stable control loop has a gain crossing with close to a
-20dB/decade slope and a phase margin greater than 45°.
Include worst case component variations when determining
phase margin. The mathematical model presented makes a
number of approximations and is generally not accurate at
frequencies approaching or exceeding half the switching
14
FN6538.2
December 2, 2008