ISL6341 Datasheet, PDF (12/17 Pages) Intersil Corporation – 5V or 12V Single Synchronous Buck Pulse-Width Modulation (PWM) Controller

ISL6341, ISL6341A, ISL6341B, ISL6341C
repeated. If V_OUT = 0.8V, then R_OFFSET can be left open.
Output voltages less than 0.8V are not available.
V_OUT=
0.8V •
(_---R_{----S-----+-----}R_-----O-----)
R_O
R_O
=
-----^R----^S-----^•----⁰----^.--⁸---^V-------
V_OUT – 0.8V
(EQ. 2)
The VOS pin is expected to see the same ratio for its resistor
divider; R_VOS1 should also be chosen in the 1kΩ to 5kΩ
(±1% for accuracy) range. To simplify the BOM, R_VOS1
should match R_S, and R_VOS2 should match R_OFFSET.
If margining (or similar programmability) is added externally
(using a switch to change the effective lower resistor value),
the same method may be needed on the VOS pin resistor
divider. If the new VOUT (FB) is shifted too much compared
to the VOS trip, then PGOOD or UV/OV will be more likely to
trip in one direction (and less likely in the other).
Input Voltage Considerations
The “Typical Application” diagram on page 3 shows a
standard configuration where V_CC is 5V to 12V, which
includes the standard 5V (±10%) or 12V (±20%) power
supply ranges. The gate drivers use the V_CC voltage for
LGATE, and V_GD (also 5V to 12V) for BOOT/UGATE. There
is an internal 5V regulator for bias.
The V_IN to the upper MOSFET can share the same supply
as V_CC, but can also run off a separate supply or other
sources, such as outputs of other regulators. If V_CC powers
up first, and the V_IN or V_GD are not present by the time the
initialization is done, then undervoltage will trip at the end of
soft-start (and will not recover without toggling V_CC; toggling
COMP/EN will not restart it). Therefore, either the supplies
must be turned on in the proper order (together, or V_CC last),
or the COMP/EN pin should be used to disable V_OUT until all
supplies are ready.
Figure 10 shows a simple sequencer for this situation. If V_CC
powers up first, Q₁ will be off and R₃ pulling to V_CC will turn
Q₂ on, keeping the ISL6341x in shut-down. When V_IN turns
on, the resistor divider R₁ and R₂ determines when Q₁ turns
on, which will turn off Q₂, and release the shut-down.
V_IN
V_CC
R₃
R₁
TO COMP/EN
R₂
Q₁
Q₂
FIGURE 10. SEQUENCER CIRCUIT
If V_IN powers up first, Q₁ will be on, turning Q₂ off; so the
ISL6341x will start-up as soon as V_CC comes up. The
V_ENABLE trip point is 0.7V nominal, so a wide variety of
NFET’s or NPN’s or even some logic IC’s can be used as Q₁
or Q₂. But Q₂ should pull down hard when on, and must be
low leakage when off (open-drain or open-collector) so as
not to interfere with the COMP output. The V_th (or V_be) of Q₂
should be reviewed over process and temperature variations
to insure that it will work properly under all conditions. Q₂
should be placed near the COMP/EN pin.
The V_IN range can be as low as ~1.5V (for V_OUT as low as
the 0.8V reference). It can be as high as 20V (for V_OUT just
below V_IN, limited by the maximum duty cycle). There are
some restrictions for running high V_IN voltage.
The first consideration for high V_IN is the maximum BOOT
voltage of 36V. The V_IN (as seen on PHASE) plus V_GD (boot
voltage - minus the diode drop), plus any ringing (or other
transients) on the BOOT pin must be less than 36V. If V_IN is
20V, that limits V_GD plus ringing to 16V.
The second consideration is the maximum voltage ratings
for V_CC and BOOT-PHASE (for V_GD); both are set at 15V. If
V_IN is above the maximum operating range for V_CC of
14.4V, then both V_CC and V_GD need to be supplied
separately. They can be derived from V_IN (using a linear
regulator or equivalent), or they can be independent. In
either case, they must satisfy the power supply sequencing
requirements noted earlier (either power-up in the proper
order, or use a sequencer to disable the output until they are
all ready).
The third consideration for high V_IN is duty cycle. Very low
duty cycles (such as 20V in to 1.0V out, for 5% duty cycle)
require component selection compatible with that choice
(such as low r_DS(ON) lower MOSFET, a good LC output
filter, and compensation values to match). At the other
extreme (for example, 20V in to 12V out), the upper
MOSFET needs to be lower r_DS(ON). There is also the
maximum duty cycle restriction. In all cases, the input and
output capacitors and both MOSFETs must be rated for the
voltages present.
Application Guidelines
Layout Considerations
As in any high frequency switching converter, layout is very
important. Switching current from one power device to another
can generate voltage transients across the impedances of the
interconnecting bond wires and circuit traces. These
interconnecting impedances should be minimized by using
wide, short printed circuit traces. The critical components
should be located as close together as possible, using ground
plane construction or single point grounding.
12
FN6538.2
December 2, 2008