ISL59483 Datasheet, PDF (14/17 Pages) Intersil Corporation – Dual, 500MHz Triple, Multiplexing Amplifiers

ISL59483
V+ SUPPLY
LOGIC
POWER
GND
SIGNAL
DE-COUPLING
CAPS
V- SUPPLY
SCHOTTKY
PROTECTION
V+
S0
GND
V- V+
IN0 V+
V-
IN1
V-
V+
LOGIC
CONTROL
V-
V+
OUT
V-
EXTERNAL
CIRCUITS
FIGURE 43. SCHOTTKY PROTECTION CIRCUIT
If positive voltages are applied to the logic or analog video
input pins before V+ is applied, current will flow through the
internal ESD diodes to the V+ pin. The presence of large
decoupling capacitors and the loading effect of other circuits
connected to V+ can result in damaging currents through the
ESD diodes and other active circuits within the device.
Therefore, adequate current limiting on the digital and
analog inputs is needed to prevent damage during the time
the voltages on these inputs are more positive than V+.
HIZ State
Each internal 4:1 triple MUX-amp has a high impedance
output control pin (HIZ1 and HIZ2). Each has an internal pull-
down resistor to set the output to the enabled state with no
connection to the HIZ pin. The HIZ state is established within
approximately 15ns by placing a logic high (>2V) on the HIZ
pin. If the HIZ state is selected, the MUX 1 output is a high
impedance 1.4MΩ with approximately 1.5pF in parallel with a
10μA bias current from the output. In the HIZ state the MUX 2
output impedance is ~900Ω. The supply current during this
state is the same as the active state.
EN and Power-down States
The EN pin is active low. An internal pull-down resistor
ensures the device will be active with no connection to the
EN pin. The power-down state is established within
approximately 80ns if a logic high (>2V) is placed on the EN
pin. In the power-down state, supply current is reduced
significantly by shutting the three amplifiers off. The output
presents a high impedance to the output pin, however, there
is a risk that the disabled amplifier output can be back-driven
at signal voltage levels exceeding ~2V_P-P. Under this
condition, large incoming slew rates can cause fault currents
of tens of mA. Therefore, the parallel connection of multiple
outputs is not recommended unless the application can
tolerate the limited power-down output impedance.
Output Capacitive Loading Considerations
High speed amplifiers may be sensitive to capacitance at the
output. Excessive pulse overshoot may result from the
combination of output slew rates approaching the amplifier
maximum and the presence of parasitic capacitance. In
applications where high slew rates are expected and PC board
output pin capacitance exceeds ~5pF, series connected
resistors (ranging from 10Ω to 75Ω) may be needed close to
the output pin in order to buffer the amplifer output stage from
the effects of capacitive loading. When paralleling the
amplifier outputs, resistance in series with MUX 1 output will
form a resistor divider with the 900Ω HIZ impedance of MUX 2
when MUX 1 is enabled and MUX 2 is in the HIZ state.
However, resistance in series with MUX 2 does not result in a
resistor divider with MUX 1 due to the 1.4MΩ HIZ impedance.
In all cases, series resistance will form a voltage divider with
any downstream load resistance, therefore the effects of
series resistance on throughput gain must be considered.
Limiting the Output Current
No output short circuit current limit exists on these parts. All
applications need to limit the output current to less than
50mA. Adequate thermal heat sinking of the parts is also
required.
PC Board Layout
The AC performance of this circuit depends greatly on the
care taken in designing the PC board. The following are
recommendations to achieve optimum high frequency
performance from your PC board.
• The use of low inductance components such as chip
resistors and chip capacitors is strongly recommended.
• Minimize signal trace lengths. Trace inductance and
capacitance can easily limit circuit performance. Avoid
sharp corners. Use rounded corners when possible. Vias
in the signal lines add inductance at high frequency and
should be avoided. PCB traces greater than 1" begin to
exhibit transmission line characteristics with signal rise/fall
times of 1ns or less. High frequency performance may be
degraded for traces greater than one inch, unless
controlled impedance (50Ω or 75Ω) strip lines or
microstrips are used.
• Match channel to channel analog I/O trace lengths and
layout symmetry. This will minimize propagation delay
mismatches.
• Maximize use of AC de-coupled PCB layers. All signal I/O
lines should be routed over continuous ground planes (i.e.
no split planes or PCB gaps under these lines). Avoid vias
in the signal I/O lines.
14
FN6394.1
December 22, 2006