ISL22323_15 Datasheet, PDF (14/19 Pages) Intersil Corporation – Low Noise, Low Power, I2C® Bus, 256 Taps

ISL22323
SCL
SDA
START
DATA
DATA
DATA
STABLE CHANGE STABLE
STOP
FIGURE 16. VALID DATA CHANGES, START AND STOP CONDITIONS
SCL FROM
MASTER
1
SDA OUTPUT FROM
TRANSMITTER
8
9
HIGH IMPEDANCE
SDA OUTPUT FROM
RECEIVER
HIGH IMPEDANCE
START
FIGURE 17. ACKNOWLEDGE RESPONSE FROM RECEIVER
ACK
SIGNALS FROM
THE MASTER
S
WRITE
T
A
R
T
IDENTIFICATION
BYTE
ADDRESS
BYTE
S
DATA
T
BYTE
O
P
SIGNAL AT SDA
1 0 1 0 A2 A1 A0 0 0 0 0 0
SIGNALS FROM
THE SLAVE
A
A
A
C
C
C
K
K
K
FIGURE 18. BYTE WRITE SEQUENCE
S
S
SIGNALS T
T
FROM THE
MASTER
A IDENTIFICATION
R
BYTE WITH
T
R/W = 0
ADDRESS
BYTE
A IDENTIFICATION
R _{BYTE WITH}
T
R/W = 1
A
C
K
SIGNAL AT SDA 1 0 1 0 A2A1 A0 0
0000
A
SIGNALS FROM
C
THE SLAVE
K
1 0 1 0 A2 A1 A0 1
A
A
C
C _{FIRST READ}
K
K _{DATA BYTE}
FIGURE 19. READ SEQUENCE
14
A
C
K
S
AT
CO
KP
LAST READ
DATA BYTE
FN6422.2
August 17, 2015