ISL22323_15 Datasheet, PDF (13/19 Pages) Intersil Corporation – Low Noise, Low Power, I2C® Bus, 256 Taps

ISL22323
TABLE 1. MEMORY MAP (Continued)
ADDRESS
(hex)
NON-VOLATILE
VOLATILE
7
General Purpose
N/A
6
General Purpose
N/A
5
General Purpose
N/A
4
General Purpose
N/A
3
General Purpose
N/A
2
General Purpose
N/A
1
IVR1
WR1
0
IVR0
WR0
The non-volatile IVRi and volatile WRi registers are
accessible with the same address.
The Access Control Register (ACR) contains information
and control bits described in Table 2.
The VOL bit (ACR[7]) determines whether the access to
wiper registers WRi or initial value registers IVRi.
TABLE 2. ACCESS CONTROL REGISTER (ACR)
BIT # 7
6
5
4
3
2
1
0
NAME VOL SHDN WIP 0
0
0
0
0
If VOL bit is 0, the non-volatile IVRi registers are accessible.
If VOL bit is 1, only the volatile WRi are accessible.
Note: value is written to IVRi register also is written to the
corresponding WRi. The default value of this bit is 0.
The SHDN bit (ACR[6]) disables or enables Shut-down mode.
When this bit is 0, DCPs are in Shut-down mode. Default value
of the SHDN bit is 1.
RHi
RWi
RLi
FIGURE 15. DCP CONNECTION IN SHUT-DOWN MODE
The WIP bit (ACR[5]) is a read-only bit. It indicates that
non-volatile write operation is in progress. It is impossible to
write to the WRi or ACR while WIP bit is 1.
I²C Serial Interface
The ISL22323 supports an I²C bidirectional bus oriented
protocol. The protocol defines any device that sends data
onto the bus as a transmitter and the receiving device as the
receiver. The device controlling the transfer is a master and
the device being controlled is the slave. The master always
initiates data transfers and provides the clock for both
transmit and receive operations. Therefore, the ISL22323
operates as a slave device in all applications.
All communication over the I²C interface is conducted by
sending the MSB of each byte of data first.
Protocol Conventions
Data states on the SDA line must change only during SCL
LOW periods. SDA state changes during SCL HIGH are
reserved for indicating START and STOP conditions (see
Figure 16). On power-up of the ISL22323, the SDA pin is in
the input mode.
All I²C interface operations must begin with a START
condition, which is a HIGH to LOW transition of SDA while
SCL is HIGH. The ISL22323 continuously monitors the SDA
and SCL lines for the START condition and does not
respond to any command until this condition is met (see
Figure 16). A START condition is ignored during the
power-up of the device.
All I²C interface operations must be terminated by a STOP
condition, which is a LOW to HIGH transition of SDA while
SCL is HIGH (see Figure 16). A STOP condition at the end
of a read operation, or at the end of a write operation places
the device in its standby mode.
An ACK (Acknowledge) is a software convention used to
indicate a successful data transfer. The transmitting device,
either master or slave, releases the SDA bus after
transmitting eight bits. During the ninth clock cycle, the
receiver pulls the SDA line LOW to acknowledge the
reception of the eight bits of data (see Figure 17).
The ISL22323 responds with an ACK after recognition of a
START condition followed by a valid Identification Byte, and
once again after successful receipt of an Address Byte. The
ISL22323 also responds with an ACK after receiving a Data
Byte of a write operation. The master must respond with an
ACK after receiving a Data Byte of a read operation
A valid Identification Byte contains 1010 as the four MSBs,
and the following three bits matching the logic values
present at pins A2, A1 and A0. The LSB is the Read/Write
bit. Its value is “1” for a Read operation and “0” for a Write
operation (See Table 3).
TABLE 3. IDENTIFICATION BYTE FORMAT
LOGIC VALUES AT PINS A2, A1 AND A0, RESPECTIVELY
1
0
1
0
A2
A1
A0 R/W
(MSB)
(LSB)
13
FN6422.2
August 17, 2015