HIP7030A2 Datasheet, PDF (14/56 Pages) Intersil Corporation – J1850 8-Bit 68HC05 Microcontroller

HIP7030A2
CPU Registers
The CPU contains five registers, as shown in the program-
ming model of Figure 9. The interrupt stacking order is
shown in Figure 10.
Accumulator (A)
The accumulator is an 8-bit general purpose register used to
hold operands, results of the arithmetic calculations, and
data manipulations.
Index Register (X)
The X register is an 8-bit register which is used during the
indexed modes of addressing. It provides an 8-bit value
which is used to create an effective address. The index reg-
ister is also used for data manipulations with the read-mod-
ify-write type of instructions and as a temporary storage
register when not performing addressing operations.
Program Counter (PC)
The program counter is a 13-bit register that contains the
address of the next instruction to be executed by the processor.
Stack Pointer (SP)
The stack pointer is a 13-bit register containing the address
of the next free locations on the pushdown/popup stack.
When accessing memory, the most significant bits are per-
manently configured to 0000011. These bits are appended
to the six least significant register bits to produce an address
within the range of $00FF to $00C0. The stack area of RAM
is used to store the return address on subroutine calls and
the machine state during interrupts. During external or
power-on reset, and during a reset stack pointer (RSP)
instruction, the stack pointer is set to its upper limit ($00FF).
Nested interrupt and/or subroutines may use up to 64 (deci-
mal) locations. When the 64 locations are exceeded, the
stack pointer wraps around and points to its upper limit
($00FF), thus, losing the previously stored information. A
subroutine call occupies two RAM bytes on the stack, while
an interrupt uses five RAM bytes.
Since the Stack Pointer decrements during pushes, the PCL
is stacked first, followed by PCH, etc. Pulling from the stack
is in the reverse order.
Condition Code Register (CC)
The condition code register is a 5-bit register which indicates
the results of the instruction just executed as well as the
state of the processor. These bits can be individually tested
by a program and specified action taken as a result of their
state. Each bit is explained in the following paragraphs.
Half Carry Bit (H)
The H bit is set to a one when a carry occurs between bits 3
and 4 of the ALU during an ADD or ADC instruction. The H
bit is useful in binary coded decimal subroutines.
Interrupt Mask Bit (I)
When the I-bit is set, all interrupts are disabled. Clearing this
bit enables the interrupts. If an external interrupt occurs
while the I-bit is set, the interrupt is latched and processed
after the I-bit is next cleared; therefore, no interrupts are lost
because of the I-bit being set. An internal interrupt can be
lost if it is cleared while the I-bit is set (refer to Programmable
Timer, Serial Communications Interface, and Serial Periph-
eral Interface Sections for more information).
Negative (N)
When set, this bit indicates that the result of the last arith-
metic, logical, or data manipulation is negative (bit 7 in the
result is a logic one).
Zero (Z)
When set, this bit indicates that the result of the last arith-
metic, logical, or data manipulation is zero.
Carry/Borrow (C)
Indicates that a carry or borrow out of the arithmetic logic
unit (ALU) occurred during the last arithmetic operation. This
bit is also affected during bit test and branch instructions,
shifts, and rotates.
Built-In-Test (BIT)
The BIT test routines utilize the SPI interface of the
HIP7030A2 to provide an efficient method to test devices,
both at the component and board level. The BIT routines are
invoked by resetting the HIP7030A2 while applying 9V_DC
(through a 4.7kΩ resistor) to the IRQ pin and 5V_DC to the
TCAP pin. After reset, the HIP7030A2 will begin executing
the BIT code stored at locations $1F00-$1FF1. The COP
system remains active during BIT. When the BIT program
begins, the SPI is configured in the master mode. SPI trans-
fers are therefore controlled by the HIP7030A2. The tester
paces the transfers by driving the IRQ line low to initiate a
SPI transfer. When the transfer is complete, the tester raises
IRQ (to 5-9V_DC) to signal successful transfer and to prepare
for the next transfer. A convenient means of driving the IRQ
pin is to connect it to 9V_DC through a 4.7kΩ resistor and to
drive it with an open-collector/collector device such as the
collector of an NPN device with its emitter grounded.
Following reset, the HIP7030A2 waits for a command to be
received from the tester by monitoring the IRQ line and the
SPIF flag in the SSR. SS should normally be held high
throughout the BIT procedure. If SS is low following reset,
the BIT routine will immediately branch to location $5D and
begin executing the program stored there.
There are five BIT functions which are accessible via the
SPI. Each is selected by sending the associated command
number to the HIP7030A2. Following completion of each
command (except Command $00), the HIP7030A2 waits for
another command. Commands outside of the range $00-$04
will be ignored.
Download (Command $00):
Download takes 175 bytes from the SPDR and writes them
to RAM beginning at $50 and ending and $FE. After receiv-
ing the 175th byte, the program begins executing at location
$5D. The 13 locations $50-$5C are used as a link table to
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