HIP7030A2 Datasheet, PDF (1/56 Pages) Intersil Corporation – J1850 8-Bit 68HC05 Microcontroller

HIP7030A2
ADVANCE INFORMATION
August 1996
J1850 8-Bit 68HC05 Microcontroller
Features
• Fully Supports VPW Specifications of SAE J1850
Standard for Class B Data Communications Network
Interface
• On-Chip Memory
• 176 Bytes of RAM
• 2110 Bytes of User ROM
• 13 Bidirectional I/O Lines
• 16-Bit Timer with Capture and Compare Registers
• Serial Peripheral Interface (SPI) System
• Watchdog Timer and Slow Clock Detect
• 10MHz Operating Frequency (5.0MHz Internal Bus
Frequency) at 5V
• Built-In-Test Bootstrap Mode with 242 Bytes of ROM
• Two Channel Analog Comparator
• On-Chip Oscillator Amplifier
• 8-Bit CPU Architecture
• Power-Saving STOP, WAIT and Data Retention Modes
• Full -40^oC to 125^oC Operating Range
• Single 3.0V to 6.0V Supply
• 28 Lead Dual-In-Line and Small Outline Plastic Pack-
ages
Software Features
• Standard 68HC05 Instruction Set
• True Bit Manipulation
• Addressing Modes Include Indexed Addressing
- Memory Mapped I/O
Ordering Information
PART NUMBER
HIP7030A2P
HIP7030A2M
TEMP.
RANGE (^oC)
PACKAGE
-40 to 125 28 Lead Plastic
DIP
-40 to 125 28 Lead Plastic
SOIC (W)
PKG.
NO.
M28.3
E28.6
Description
The HIP7030A2 HCMOS Microcomputer is a member of the
CDP68HC05 family of low-cost single-chip microcomputers.
The integrated hardware functions provide the system
designer with a complete set of building blocks for
implementing a “Class B” multiplexed communications net-
work interface, which fully conforms to the VPW Multiplexed
Wiring protocol specified in SAE Recommended Practice
J1850. This 8-bit microcomputer unit (MCU) contains an on-
chip oscillator, CPU, 176 bytes of RAM, 2110 bytes of user
ROM, 13 I/O lines, a J1850 Variable Pulse Width Symbol
Encoder/Decoder (VPW SENDEC) system, a Serial Periph-
eral Interface (SPI) system, a two channel analog Compara-
tor, a Watchdog Timer, a Slow Clock Detect, and a 16-bit
Timer. The static HCMOS design allows operation at input
frequencies up to 10MHz (5MHz internal clock).
Table of Contents
Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
MCU Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
Electrical & Timing Specifications . . . . . . . . . . . . . . . . . . . . . 3
Functional Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Integrated Hardware I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Built-In Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Vector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Programmable Timer
Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . 27
J1850 VPW Messaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Symbol Encoder Decoder
Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
COP System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Effects of STOP and WAIT Modes . . . . . . . . . . . . . . . . . . . . 41
Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Package Outline Dimensions . . . . . . . . . . . . . . . . . . . . 55 - 56
Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
I/O, Control, Status and Data Register Definitions . . . . . . . 52
Ordering
Information Sheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Ordering Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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File Number 3646.2