HC55185_06 Datasheet, PDF (14/20 Pages) Intersil Corporation – VoIP Ringing SLIC Family

HC55185
When operating from a battery of -100V, each amplifier, Tip
and Ring, will swing a maximum of 95V_P-P. Hence, the
maximum signal swing at VRS to achieve full scale ringing is
approximately 2.4V_P-P. The low signal levels are compatible
with the output voltage range of the CODEC. The digital
nature of the CODEC ideally suits it for the function of
programmable ringing generator. See Applications Section.
Logic Control
Ringing patterns consist of silent intervals. The ringing to
silent pattern is called the ringing cadence. During the silent
portion of ringing, the device can be programmed to any
other operating mode. The most likely candidates are low
power standby or forward active. Depending on system
requirements, the low or high battery may be selected.
Loop supervision is provided with the ring trip detector. The ring
trip detector senses the change in loop current when the phone
is taken off hook. The loop detector full wave rectifies the
ringing current, which is then filtered with external components
R_RT and C_RT. The resistor R_RT sets the trip threshold and the
capacitor C_RT sets the trip response time. Most applications will
require a trip response time less than 150ms.
Three very distinct actions occur when the devices detects a
ring trip. First, the DET output is latched low. The latching
mechanism eliminates the need for software filtering of the
detector output. The latch is cleared when the operating
mode is changed externally. Second, the VRS input is
disabled, removing the ring signal from the line. Third, the
device is internally forced to the forward active mode.
Power Dissipation
The power dissipation during ringing is dictated by the load
driving requirements and the ringing waveform. The key to valid
power calculations is the correct definition of average and RMS
currents. The average current defines the high battery supply
current. The RMS current defines the load current.
The cadence provides a time averaging reduction in the
peak power. The total power dissipation consists of ringing
power, P_r, and the silent interval power, P_s.
P_RNG=
P_r ×
------^t--^r-----
t_r + t_s
+
P_s
×
------^t-^s------
t_r + t_s
(EQ. 35)
The terms t_R and t_S represent the cadence. The ringing
interval is t_R and the silent interval is t_S . The typical cadence
ratio t_R:t_S is 1:2.
The quiescent power of the device in the ringing mode is
defined in Equation 36.
P_r(Q) = V_BH × I_BHQ + V_BL × I_BLQ + V_CC × I_CCQ
(EQ. 36)
The total power during the ringing interval is the sum of the
quiescent power and loading power:
P_r
=
P_r(Q)
+
V_BH
×
I_AVG
–
-------------^V-----^R2----^M-----^S--------------
Z_REN + R_LOOP
(EQ. 37)
For sinusoidal waveforms, the average current, I_AVG, is
defined in Equation 38.
I_AVG=
⎛
⎝
2_{π--⎠⎞}
-------^V----^R----^M-----^S-----^×---------²-------
Z_REN + R_LOOP
(EQ. 38)
The silent interval power dissipation will be determined by
the quiescent power of the selected operating mode.
Unbalanced Ringing
The HC55185GCM offers a new Unbalanced Ringing mode
(010). This feature has been added to accommodate some
Analog PBX Trunk Lines that require the Tip terminal to be
held near ground for the duration of the ringing bursts. The
Tip terminal is offset to 0V’s with an internal current source
that is applied to the inverting input of the Tip amplifier. This
reduces the differential ringing gain to 40V/V. The Ring
terminal will center at Vbh/2 and swing from -Vbh to ground.
As in Balanced Ringing, off hook detection is accomplished
by sensing the peak current and comparing it to a preset
threshold. This allows the same sensing, comparing and
threshold circuitry to be used in both Ringing modes. This
mode of operation does not require any additional external
components.
Forward Loop Back
Overview
The Forward Loop Back mode (FLB, 101) provides test
capability for the device. An internal signal path is enabled
allowing for both DC and AC verification. The internal 600Ω
terminating resistor has a tolerance of ±20%. The device is
intended to operate from only the low battery during this
mode.
Architecture
When the forward loop back mode is initiated internal
switches connect a 600Ω load across the outputs of the Tip
and Ring amplifiers.
TIP
RING
600Ω
TIP AMP
RING AMP
FIGURE 11. FORWARD LOOP BACK INTERNAL TERMINATION
DC Verification
When the internal signal path is provided, DC current will
flow from Tip to Ring. The DC current will force DET low,
indicating the presence of loop current. In addition, the ALM
output will also go low. This does not indicate a thermal
alarm condition. Rather, proper logic operation is verified in
the event of a thermal shutdown. In addition to verifying
device functionality, toggling the logic outputs verifies the
interface to the system controller.
14
FN4831.14
December 18, 2006