X5168 Datasheet, PDF (13/19 Pages) Intersil Corporation – CPU Supervisor with 16Kbit SPI EEPROM

Serial Input Timing
CS
SCK
SI
t_LEAD
t_SU
t_H
MSB IN
X5168, X5169
t_RI
t_CS
t_LAG
t_FI
LSB IN
High Impedance
SO
Serial Output Timing
SYMBOL
f_SCK
t_DIS
t_V
t_HO
t_RO(3)
t_FO(3)
PARAMETER
Clock frequency
Output disable time
Output valid from clock low
Output hold time
Output rise time
Output fall time
2.7-5.5V
MIN
MAX
0
2
250
200
0
100
100
UNIT
MHz
ns
ns
ns
ns
ns
Notes: (3) This parameter is periodically sampled and not 100% tested.
(4) t_WC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile
write cycle.
Serial Output Timing
CS
SCK
SO
t_CYC
t_WH
t_LAG
t_V
MSB Out
t_HO
MSB–1 Out
t_WL
t_DIS
LSB Out
SI
ADDR
LSB IN
13
FN8130.1
September 16, 2005