ISL6611A Datasheet, PDF (13/14 Pages) Intersil Corporation – Phase Doubler with Integrated Drivers Phase Doubler with Integrated Drivers

ISL6611A
part, connect it to the adjacent net (LGATE2/PHASE2) can
reduce trace inductance.
• Shorten all gate drive loops (UGATE-PHASE and
LGATE-PGND) and route them closely spaced.
• Minimize the inductance of the PHASE node. Ideally, the
source of the upper and the drain of the lower MOSFET
should be as close as thermally allowable.
• Minimize the current loop of the output and input power
trains. Short the source connection of the lower MOSFET
to ground as close to the transistor pin as feasible. Input
capacitors (especially ceramic decoupling) should be
placed as close to the drain of upper and source of lower
MOSFETs as possible.
• Avoid routing relatively high impedance nodes (such as
PWM and ENABLE lines) close to high dV/dt UGATE and
PHASE nodes.
In addition, connecting the thermal pad of the QFN package
to the power ground through multiple vias, or placing a low
noise copper plane (such as power ground) underneath the
SOIC part is recommended. This is to improve heat
dissipation and allow the part to achieve its full thermal
potential.
Upper MOSFET Self Turn-On Effects At Start-up
Should the driver have insufficient bias voltage applied, its
outputs are floating. If the input bus is energized at a high
dV/dt rate while the driver outputs are floating, due to the
self-coupling via the internal C_GD of the MOSFET, the
UGATE could momentarily rise up to a level greater than the
threshold voltage of the MOSFET. This could potentially turn
on the upper switch and result in damaging in-rush energy.
Therefore, if such a situation (when input bus powered up
before the bias of the controller and driver is ready) could
conceivably be encountered, it is common practice to place
a resistor (R_UGPH) across the gate and source of the upper
MOSFET to suppress the Miller coupling effect. The value of
the resistor depends mainly on the input voltage’s rate of
rise, the C_GD/C_GS ratio, as well as the gate-source
threshold of the upper MOSFET. A higher dV/dt, a lower
C_DS/C_GS ratio, and a lower gate-source threshold upper
FET will require a smaller resistor to diminish the effect of
the internal capacitive coupling. For most applications, the
integrated 20kΩ typically sufficient, not affecting normal
performance and efficiency.
The coupling effect can be roughly estimated with the
equations in Equation 7, which assume a fixed linear input
ramp and neglect the clamping effect of the body diode of
the upper drive and the bootstrap capacitor. Other parasitic
components such as lead inductances and PCB
capacitances are also not taken into account. These
equations are provided for guidance purposes only. Thus,
the actual coupling effect should be examined using a very
high impedance (10MΩ or greater) probe to ensure a safe
design margin.
⎛
----------–---^V----^D-----^S-----------⎞
V_{G S _MILLER}
=
d_----V_---
dt
⋅
R
⋅
C_r
ss
⎜
⎜
⎜
⎜
1
–
e
d_----V_---
dt
⋅
R
⋅
Ci
⎟
s s⎟
⎟
⎟
⎝
⎠
(EQ. 7)
R = R_UGPH + R_GI
C_rss = C_GD
C_iss = C_GD + C_GS
VCC
DU
DL
BOOT
C_BOOT
C_GD
VIN
D
UGATE G
R_GI
C_DS
PHASE
C_GS
S
Q_UPPER
FIGURE 9. GATE TO SOURCE RESISTOR TO REDUCE
UPPER MOSFET MILLER COUPLING
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13
FN6881.0
March 19, 2009