ISL6611A Datasheet, PDF (11/14 Pages) Intersil Corporation – Phase Doubler with Integrated Drivers Phase Doubler with Integrated Drivers

ISL6611A
PVCC
BOOT
R_HI1
R_LO1
UGATE
PHASE
C_GD
G
R_G1
R_GI1
C_GS
S
D
C_DS
Q1
FIGURE 3. TYPICAL UPPER-GATE DRIVE TURN-ON PATH
PVCC
R_HI2 ^LGATE
R_LO2
GND
C_GD
G
R_G2
R_GI2
C_GS
S
D
C_DS
Q2
FIGURE 4. TYPICAL LOWER-GATE DRIVE TURN-ON PATH
EN_PH Operation
EN_PH
PWM
UGATE
LGATE
FIGURE 5. TYPICAL EN_PH OPERATION TIMING DIAGRAM
The ISL6611A disables the phase doubler operation when the
EN_PH pin is pulled to ground and after it sees the PWM
falling edge. The PWM pin is pulled to VCC at the PWM falling
edge. With the PWM line pulled high, the controller will disable
the corresponding phase and the higher number phases.
When the EN_PH is pulled high, the phase doubler will pull
the PWM line to tri-state and then will be enabled at the
leading edge of PWM input. Prior to a leading edge of PWM, if
the PWM is low, both LGATEA and LGATEB remain in tri-
state unless the corresponding phase node (PHASEA,
PHASEB) is higher than 80% of VCC. This provides additional
protection if the doubler is enabled while the high-side
MOSFET is shorted. However, this feature limits the
pre-charged output voltage to less than 80% of VCC. Note
that the first doubler should always tie its EN_PH pin high
since Intersil controllers do not allow PWM1 pulled high and
this channel should remain ON to protect the system from an
overvoltage event even when the controller is disabled.
SYNC Operation
The ISL6611A can be set to interleaving mode or
synchronous mode by pulling the SYNC pin to GND or VCC,
respectively. A synchronous pulse can be sent to the phase
doubler during the load application to improve the voltage
droop and current balance while it still can maintain
interleaving operation at DC load conditions. However, an
excessive ringback can occur; hence, the synchronous
mode operation could have drawbacks. Figure 6 shows how
to generate a synchronous pulse only when an transient
load is applied. The comparator should be a fast comparator
with a minimum delay.
20kΩ
2kΩ
COMP
49.9kΩ
+
-
1.0 nF
VCC
0Ω
1kΩ
SYNC
DNP
FIGURE 6. TYPICAL SYNC PULSE GENERATOR
Current Balance and Maximum Frequency
The ISL6611A utilizes r_DS(ON) sensing technique to balance
both channels, while the sample and hold circuits refer to
GND pin. The phase current sensing resistors are
integrated, while the current gain can be scaled by the
impedance on the IGAIN pin, as shown in Table 1. In most
applications, the default option should just work fine.
TABLE 1. CURRENT GAIN SELECTION
IMPEDANCE TO GND
CURRENT GAIN
OPEN
0Ω
DEFAULT
DEFAULT/2
49.9kΩ
DEFAULT/5
In addition to balancing the effective UGATE pulse width of
phase A and phase B via standard r_DS(ON) current sensing
technique, a fast path is also added to swap both channels’
firing order when one phase carries much higher current
than the other phase. This improves the current balance
between phase A and phase B during high frequency load
transient events.
Each phase starts to sample current 200ns (t_BLANK) after
LGATE falls and lasts for 400ns (t_SAMP) or ends at the rising
edge of PWM if the available sampling time (t_AVSAMP) is
< 400ns. The available sampling time (t_AVSAMP) depends
upon the blanking time (t_BLANK), the duty cycle (D), the
rising and falling time of low-side gate drive (t_LR, t_LF), the
total propagation delay (t_PD = t_PDLL + t_PDLU), and the
switching frequency (F_SW). As the switching frequency and
the duty cycle increase, the available sampling time could be
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FN6881.0
March 19, 2009