ISL6423B Datasheet, PDF (13/16 Pages) Intersil Corporation – Single Output LNB Supply and Control Voltage Regulator with I2C Interface for Advanced Satellite Set-Top Box Designs

TABLE 10. CONTROL REGISTER SR4 CONFIGURATION
SR4H SR4M SR4L EN
X
X VTOP VBOT
FUNCTION
0
1
1
1
X
X
0
0 SR4 is selected
0
1
1
1
X
X
0
0 VSPEN = SELVTOP = 0, V_OUT = 13V, V_BOOST = 13V + V_DROP
0
1
1
1
X
X
0
1 VSPEN = SELVTOP = 0, V_OUT = 14V, V_BOOST = 14V + V_DROP
0
1
1
1
X
X
1
0 VSPEN = SELVTOP = 0, V_OUT = 13V, V_BOOST = 13V + V_DROP
0
1
1
1
X
X
1
1 VSPEN = SELVTOP = 0, V_OUT = 14V, V_BOOST = 14V + V_DROP
0
1
1
1
X
X
0
0 VSPEN = 0,SELVTOP = 1, V_OUT = 18V, V_BOOST = 18V + V_DROP
0
1
1
1
X
X
0
1 VSPEN = 0,SELVTOP = 1, V_OUT = 18V, V_BOOST = 18V + V_DROP
0
1
1
1
X
X
1
0 VSPEN = 0,SELVTOP = 1, V_OUT = 19V, V_BOOST = 19V + V_DROP
0
1
1
1
X
X
1
1 VSPEN = 0,SELVTOP = 1, V_OUT = 19V, V_BOOST = 19V + V_DROP
0
1
1
1
X
X
0
0 VSPEN = 1,SELVTOP = X V_OUT = 13V, V_BOOST = 13V + V_DROP
0
1
1
1
X
X
0
1 VSPEN = 1,SELVTOP = X V_OUT = 14V, V_BOOST = 14V + V_DROP
0
1
1
1
X
X
1
0 VSPEN = 1,SELVTOP = X V_OUT = 18V, V_BOOST = 18V + V_DROP
0
1
1
1
X
X
1
1 VSPEN = 1,SELVTOP = X V_OUT = 19V, V_BOOST = 19V + V_DROP
0
1
1
0
X
X
X
X PWM and Linear for channel 1 disabled
NOTE: X indicates “Read Only” and is a “Don’t Care” for the Write mode.
Received Data (I²C bus READ MODE)
The ISL6423B can provide to the master a copy of the
system register information via the I²C bus in read mode.
The read mode is Master activated by sending the chip
address with R/W bit set to 1. At the following Master
generated clock bits, the ISL6423B issues a byte on the
SDA data bus line (MSB transmitted first).
At the ninth clock bit the MCU master can:
• Acknowledge the reception, starting in this way the
transmission of another byte from the ISL6423B.
• Not acknowledge, stopping the read mode
communication.
The read only bits of the register SR1 convey diagnostic
information about the ISL6423B, as indicated in the Table 7.
Power–On I²C Interface Reset
The I²C interface built into the ISL6423B is automatically reset
at power-on. The I²C interface block will receive a Power OK
logic signal from the UVLO circuit. This signal will go HIGH
when chip power is OK. As long as this signal is LOW, the
interface will not respond to any I²C commands and the
system register SR1 thru SR4 are all initialized to all zero,
thus keeping the power blocks disabled. Once the V_CC rises
above UVLO, the POWER OK signal to the I²C is asserted
high, and the I²C interface becomes operative and the SR’s
can be configured by the main microprocessor. About 400mV
of hysteresis is provided in the UVLO threshold to avoid false
triggering of the Power-On reset circuit. (I²C comes up with
EN = 0; EN goes HIGH at the same time as (or later than) all
other I²C data for that PWM becomes valid).
ADDR0 and ADDR1 Pins
Connecting these pin to GND the chip I²C interface address
is 0001000, but, it is possible to choose between four
different addresses by setting these pins to the logic levels
indicated in Table 11.
TABLE 11. ADDRESS PIN CHARACTERISTICS
V_ADDR
V_ADDR-1 “0001000”
V_ADDR-2 “0001001”
V_ADDR-3 “0001010”
V_ADDR-4 “0001011”
ADDR1
0
0
1
1
ADDR0
0
1
0
1
13
FN6412.1
April 10, 2007