ISL6225 Datasheet, PDF (13/19 Pages) Intersil Corporation – Dual Mobile-Friendly PWM Controller with DDR Memory Option

ISL6225
This makes out-of-phase channel synchronization
undesirable when one of the channels is running on a duty-
factor of 50%. Inversely, the in-phase channel arrangement
does not have this drawback. Points of decision are far from
noisy moments of time in both sourcing and sinking modes
of operation for V_IN = 7.5V to 24V as it is shown in Figure 9.
In the case when power for VDDQ is taken from the +5V
system rail, as Figure 10 shows, both in-phase and out-of-
phase approaches are susceptible to noise in the sourcing
mode.
300kHz CLOCK
VDDQ
SOURCING
VTT
OUT-OF-PHASE
SINKING
SOURCING
VTT
IN-PHASE
SINKING
FIGURE 9. CHANNEL INTERFERENCE V_IN = 7.5V...24V
Noise immunity can be improved by operating the VTT
converter with a 90^o phase shift. As the time diagrams in
Figure 10 show, the points of concern are always about a
quarter of the period away from the noise emitting
transitions.
300kHz CLOCK
VDDQ
SOURCING
VTT
SINKING
SOURCING
VTT
SINKING
SOURCING
VTT
OUT-OF-PHASE
IN-PHASE
90^o PHASE SHIFT
Several ways of synchronization are implemented into the
chip. When the DDR pin is connected to GND, the channels
operate 180^o out-of-phase. In the DDR mode when the DDR
pin is connected to V_CC, the channels operate either in-
phase when the V_IN pin is connected to the input voltage
source, or with 90^o phase shift if the VIN pin is connected to
GND.
ISL6225 DC-DC Converter Application
Circuits
Figures 11 and 12 show application circuits of a dual channel
DC/DC converter for a notebook PC.
The power supply in Figure 11 provides +2.5V and +1.8V for
memory and graphic interface chipset from +5.0V to +24V
battery voltage.
Figure 12 shows the power supply that provides +2.5V and
+1.8V for memory and graphic interface chipset from +5.0V
system rail.
Figure 13 shows an application circuit for a single-output
split input power supply with current sharing for advanced
graphic card applications.
Figure 14 and 15 show application circuits of a complete
power solution for DDR memory that becomes a preferred
choice in modern computers. The power supply shown in
Figure 14 generates +2.5V VDDQ voltage from +5.0V to
+24V battery voltage. The +1.25V VTT termination voltage
tracks VDDQ/2 and is derived from +2.5V VDDQ. To
complete the DDR memory power requirements, the +1.25V
reference voltage is also provided. The PG2 pin serves as
an output for the reference voltage in this mode.
Figure 15 depicts the DDR solution in the case where the 5V
system rail is used as a primary voltage source.
For detailed information on the circuit, including a Bill-of-
Materials and circuit board description, see Application Note
AN9995. Also see Intersil’s web site (http://www.intersil.com)
for the latest information.
SINKING
FIGURE 10. CHANNEL INTERFERENCE V_IN = 5V
13
FN9049.7
December 28, 2004