ISL6186_14 Datasheet, PDF (13/18 Pages) Intersil Corporation – USB Port Power Supply Controller

ISL6186
ISL61863EVAL1Z Schematic and Photo
GND
GND
PG
*
VIN
OUT
EN FLT
NOTE: *PGD Output only available on ISL61863 types
FIGURE 28A. ISL61863EVAL1Z SCHEMATIC
FIGURE 28B. ISL61863EVAL1Z BOARD PHOTO
FIGURE 28. ISL61863EVAL1Z SCHEMATIC and ISL61863EVAL1Z PHOTOGRAPH
Application Information
Using the ISL6186XEVAL1Z Platform
General and Biasing Information
There are three evaluation platforms for the ISL6186 family.
There is one for each package style, each with a different
continuous output current level and representing a mix of enable
polarity and output retry or latch options. The standard available
evaluation board options are listed at the end of the Ordering
Information table, which starts on page 3. Figure 28A illustrates
the schematic for the 10 Ld DFN ISL61863EVAL1Z. Other than
the unique PGOOD output on the ISL61863 types, all the
schematics and functions are the same across all three package
types. Consult the individual package pinouts on page 2 for those
differences.
The evaluation platform is biased and monitored through a few
labeled test points. See Table 1 for test point assignments and
descriptions.
TABLE 1. ISL61863EVAL1Z TEST POINT ASSIGNMENTS
TP NAME
DESCRIPTION
GND
Eval Board and IC Gnd
VIN
Eval Board, IC Bias and Power Input
EN
Enable Switch
OUT
Switch Power Output
PG
Power-Good Output
FLT
Fault Output
Upon proper bias of the evaluation platform and correct enabling
of the IC, the ISL6186 will have a nominal V_IN/5.1Ω load current
that is below the continuous current rating passing through each
enabled switch. See Figures 14 to 16 for typical ISL6186 turn-on
and turn-off waveforms.
External current loading in excess of the trip current level for the
particular part being evaluated will result in the ISL6186 entering
current limiting mode. Figure 11 illustrates current limiting mode
for the ISL6186 product variants with 1.5A of continuous load
current rating. The scope shot shows current limiting for ~12ms
before it is turned off and the fault signal is asserted.
Application Considerations
See Table 2 for a listing of the ISL6186XEVAL1Z board
components.
Decoupling V_IN
Application considerations for the ISL6186 family are widely
accepted best industry practices. Good decoupling practices on
the V_IN pin must be followed by placement close to the IC, with at
least 2.2µF being recommended. For the 3.0 and 3.6A versions,
at least 33µF is recommended to prevent spiking and glitching
on V_IN during an OC event. Use good PCB layout practices to
reduce input and output inductance to the ISL6186.
Loading V_OUT
When designing with the 3A and 3.6A versions in an
implementation in which the output may be unloaded (open)
while the ISL6186 is turned on, a minimum of 4.7µF of
capacitive loading is recommended to prevent high dv/dt from
unnecessarily activating the surge/ESD circuitry.
Continuous Current Ratings
The ISL6186 provides several continuous current rated devices
specified at V_IN = 5V: these are the 1.5A, 3A and 3.6A options,
which are capable over the entire temperature extreme. At
V_IN = 3.3V, current capability is degraded, and the ISL6186 is
specified at 1.5A and 3A. At V_IN = 2.5V, there are no
specifications, but a typical value is provided in the specification
table as guidance for +25°C operation. This degraded capability
is due to the higher r_DS(ON) of the FET switch at the lower bias
voltage.
Enhanced thermal characteristics and an increased number of
bond wires allows the 10 Ld DFN to have a higher current
capability than either the 8 Ld SOIC or 8 Ld DFN.
13
FN7698.2
November 3, 2011