ISL23415 Datasheet, PDF (13/19 Pages) Intersil Corporation – Single, Low Voltage Digitally Controlled Potentiometer (XDCP™)

ISL23415
external pull-up resistor is required for Open Drain output
operation. When CS is HIGH, the SDO pin is in tri-state (Z) or
high-tri-state (Hi-Z) depends on the selected configuration.
CHIP SELECT (CS)
CS LOW enables the ISL23415, placing it in the active power
mode. A HIGH to LOW transition on CS is required prior to the
start of any operation after power-up. When CS is HIGH, the
ISL23415 is deselected and the SDO pin is at high impedance,
and the device will be in the standby state.
Principles of Operation
The ISL23415 is an integrated circuit incorporating one DCP with
its associated registers and an SPI serial interface providing
direct communication between a host and the potentiometer.
The resistor array is comprised of individual resistors connected
in series. At either end of the array and between each resistor is
an electronic switch that transfers the potential at that point to
the wiper.
The electronic switches on the device operate in a “make before
break” mode when the wiper changes tap positions.
Voltage at any DCP pins, RH, RL or RW, should not exceed V_CC
level at any conditions during power-up and normal operation.
The V_LOGIC pin needs to be connected to the SPI bus supply
which allows reliable communication with the wide range of
microcontrollers and independent of the V_CC level. This is
extremely important in systems where the digital supply has
lower levels than the analog supply.
DCP Description
Each DCP is implemented with a combination of resistor
elements and CMOS switches. The physical ends of DCP are
equivalent to the fixed terminals of a mechanical potentiometer
(RH and RL pins). The RW pin of the DCP is connected to
intermediate nodes, and is equivalent to the wiper terminal of a
mechanical potentiometer. The position of the wiper terminal
within the DCP is controlled by the 8-bit volatile Wiper Register
(WR). When the WR of a DCP contains all zeroes (WR[7:0] = 00h),
its wiper terminal (RW) is closest to its “Low” terminal (RL). When
the WR register of a DCP contains all ones (WR[7:0] = FFh), its
wiper terminal (RW) is closest to its “High” terminal (RH). As the
value of the WR increases from all zeroes (0) to all ones (255
decimal), the wiper moves monotonically from the position
closest to RL to the position closest to RH. At the same time, the
resistance between RW and RL increases monotonically, while
the resistance between RH and RW decreases monotonically.
While the ISL23415 is being powered up, the WR is reset to 80h
(128 decimal), which locates RW roughly at the center between
RL and RH.
The WR can be read or written to directly using the SPI serial
interface as described in the following sections.
Memory Description
The ISL23415 contains two volatile 8-bit registers: the Wiper
Register (WR) and the Access Control Register (ACR). Memory map
of ISL23415 is in Table 1. The Wiper Register WR at address 0
contains current wiper position of the DCP. The Access Control
Register (ACR) at address 10h contains information and control
bits described in Table 2.
ADDRESS
(hex)
10
0
TABLE 1. MEMORY MAP
VOLATILE
DEFAULT SETTING
(hex)
ACR
40
WR
80
TABLE 2. ACCESS CONTROL REGISTER (ACR)
BIT # 7
6
5
4
3
2
1
0
NAME 0 SHDN 0
0
0
0 SDO 0
The SHDN bit (ACR[6]) disables or enables Shutdown mode. When
this bit is 0, i.e., each DCP is forced to end-to-end open circuit and
each RW is shorted to RL as shown in Figure 25. Default value of
the SHDN bit is 1.
RH
RW
RL
FIGURE 25. DCP CONNECTION IN SHUTDOWN MODE
The SDO bit (ACR[1]) configures type of SDO output pin. The
default value of SDO bit is 0 for Push-Pull output. The SDO pin
can be configured as Open Drain output for some applications. In
this case, an external pull-up resistor is required, reference the
“Serial Interface Specification” on page 7.
SPI Serial Interface
The ISL23415 supports an SPI serial protocol, mode 0. The
device is accessed via the SDI input and SDO output with data
clocked in on the rising edge of SCK, and clocked out on the
falling edge of SCK. CS must be LOW during communication with
the ISL23415. The SCK and CS lines are controlled by the host or
master. The ISL23415 operates only as a slave device.
All communication over the SPI interface is conducted by
sending the MSB of each byte of data first.
Protocol Conventions
The SPI protocol contains Instruction Byte followed by one or more
Data Bytes. A valid Instruction Byte contains instruction as the three
MSBs, with the following five register address bits (see Table 3).
The next byte sent to the ISL23415 is the Data Byte.
TABLE 3. INSTRUCTION BYTE FORMAT
BIT # 7
6
5
4
3
2
1
0
I2
I1
I0 R4 R3 R2 R1 R0
Table 4 contains a valid instruction set for ISL23415.
If the [R4:R0] bits are zero, then the read or write is to the WR
register. If the [R4:R0] are 10000, then the operation is to the ACR.
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FN7780.0
December 15, 2010