ISL1903 Datasheet, PDF (13/19 Pages) Intersil Corporation – Dimmable Buck LED Driver - AC Mains or DC Input LED Driver

ISL1903
Functional Description
Features
The ISL1903 LED driver is an excellent choice for low cost AC
mains powered single conversion LED lighting applications. It
provides active power factor correction (PFC) to achieve high
power factor using critical conduction mode operation, and
incorporates additional features for compatibility with
triac-based dimmers. Furthermore, it senses FET switching
currents to regulate the output current which eliminates the need
to level shift current feedback signal, or for isolated designs, to
cross the isolation boundary to close the feedback control loop.
The ISL1903 includes support for both PWM and DC current
dimming of the output.
Oscillator
The ISL1903 uses a critical conduction mode (CrCM) algorithm to
control the switching behavior of the converter. The ON-time of
the primary power switch is held virtually constant by the low
bandwidth control loop (in PFC applications). The OFF-time
duration is determined by the time it takes the current or voltage
to decay during the flyback period. When the mmf (magneto
motive force) of the transformer decays to zero, the winding
currents are zero and the winding voltages collapse. Either may
be monitored and used to initiate the next switching cycle. The
ISL1903 monitors the CrCM condition using the CS+ signal. It
may be used to monitor either current or voltage.
Additionally, there is a user adjustable delay duration, DELADJ, to
delay the initiation of the next switching cycle to allow the
drain-source voltage of the primary switch to ring to a minimal.
This allows quasi-ZVS operation to reduce capacitive switching
losses and improve efficiency. See “Quasi-Resonant Switching”
on page 17.
By its nature the converter operation is variable frequency. There
are both minimum and maximum frequency clamps that limit
the range of operation. The minimum frequency clamp prevents
the converter from operating in the audible frequency range. The
maximum frequency clamps prevents operating at very high
frequencies that may result in excessive losses.
An individual switching period is the sum of the ON-time, the
OFF-time, and the restart delay duration. The ON-time is
determined by the control loop error voltage, VERR, and the
RAMP signal. As its name implies, the RAMP signal is a linearly
increasing signal that starts at zero volts and ramps to a
maximum of ~VERR/5 - 235mV. RAMP requires an external
resistor and capacitor connected to VREF to form an RC charging
network. If VERR is at its maximum level of VREF, the time
required to charge RAMP to ~850mV determines the maximum
ON-time of the converter. RAMP is discharged every switching
cycle when the ON-time terminates.
The OFF-time duration is determined by the design of the
magnetic element(s), which depends on the required energy
storage/transfer and the inductance of the winding(s). The
transformer/inductor design also determines the maximum
ON-time that can be supported without saturation, so, in reality,
the magnetics design is critical to every aspect of determining
the switching frequency range.
The design methodology is similar to designing a discontinuous
mode (DCM) buck converter with the constraint that it must
operate at the DCM/CCM boundary at maximum load and
minimum input voltage. The difference is that the converter will
always operate at the DCM/CCM boundary, whereas a DCM
converter will be more discontinuous as the input voltage
increases or the load decreases. In PFC applications, the design
is further complicated by the input voltage waveform, a rectified
sinewave.
Once the output power, Po, the output current, Io, the output
voltage, Vo, and the minimum input AC voltage are known, the
inductor design can be started. From the minimum AC input
voltage, the minimum DC equivalent (RMS) input voltage must
be determined. In PFC applications, the converter behaves as if
the input voltage is an equivalent DC value due to the low control
loop bandwidth.
A typical minimum operating frequency must be selected. This is
a somewhat arbitrary determination, but does ultimately
determine the inductor size. The typical frequency is what occurs
when the instantaneous rectified input AC voltage is exactly at
the equivalent DC value. The frequency will be higher when the
instantaneous input voltage is lower, and lower when the
instantaneous input voltage is higher. However, the duty cycle at
the equivalent DC input voltage determines the ON-time for the
entire AC half-cycle. The ON-time is constant due to the low
bandwidth control loop, but the OFF-time and duty cycle vary with
the instantaneous input voltage since the peak switch current
follows V = Ldi/dt.
The typical frequency may require adjustment once the initial
calculations are complete to see if the operating frequency at the
peak of the minimum AC input voltage is acceptable. The peak
current will be 1.41 times higher at the AC peak than at the DC
equivalent (RMS) input voltage. So, while the ON-time is nearly
constant due to the low bandwidth control loop, the OFF-time will
be 1.41 times longer.
The effective AC conduction angle must also be considered when
calculating the inductance. Since no current flows to the load
when the instantaneous input voltage is less than the output
voltage, the equivalent DC input voltage (rms) is duty cycle
modulated by the effective AC conduction angle. This results in
higher currents during the portion of the AC half-cycle when the
converter can deliver power to the load. The switching currents
increase and the frequency of operation decreases. Obviously the
higher the output voltage the greater the impact.
13
FN8285.1
September 20, 2012