X80070 Datasheet, PDF (12/14 Pages) Intersil Corporation – Hot Swap Controller with Advanced Fault Protection and Voltage Refulator Output

X80070, X80071, X80072, X80073
Gate Drive Output Slew Rate (Inrush Current) Control
The gate output drives an external N-Channel FET. The GATE
pin goes high when no overcurrent, undervoltage or
overvoltage conditions exist.
The X80070 provides an I_GATE current of 50uA to provide on-
chip slew rate control to minimize inrush current and provide
the best turn on time for a given load, while avoiding
overcurrent conditions.
Slew Rate (Gate) Control
As shown in Figure 11, this circuit block contains a current
source (I_GATE) that drives the 50uA current into the GATE pin.
This current provides a controlled slew rate for the FET.
To give the designer flexibility in the design of the hot swap
circuit, the X80070 provides two external pins, IGQ1 and IGQ0.
These pins allow the user to switch to different GATE currents
on-the-fly by selecting one of four pre-selected I_GATE currents.
When IGQ0 and IGQ1 are left unconnected, the gate current is
50uA. The other three settings are 10uA, 70uA and 150uA, as
shown in Table 3.
Table 3. IGQ Gate Current Selection
IGQ1
pin
0
0
1
1
IGQ0
pin
Operation
0 Defaults to gate current 50µA
1 Gate Current is 10µA
0 Gate Current is 70µA
1 Gate Current is 150µA
Typically, the delay from IGQ1 and IGQ0 selection to a change
in the GATE pin current is less than 1 µsecond.
Figure 11. Slew Rate (Inrush Current) Control
VDD
V_EE
i.e. 12V
50µA
Gate
Current
Select
Logic
Slew Rate
Logic
SENSE GATE
IGQ1
IGQ0
-48V
C1
100n
R1 ^R2
100 ^22K
R_SENSE
RDS_ON
I_INRUSH
C2
3.3nF
LOAD
Gate Capacitor, Filtering and Feedback
The FET control circuit includes an FET feedback capacitor
C₂, which provides compensation for the FET during turn on.
The capacitor value depends on the load, the choice of FET
(because of the FET internal capacitances) and the FET
gate current.
The value of C2 can be selected with the following formula.
C2 = ^I--G-----^A----^T---^E-----^×-----C-----^L---^O-----^A----^D--
I_INRUSH
Where:
I_GATE = FET Gate current
I_INRUSH = Maximum desired inrush current
C_LOAD = DC/DC bulk capacitance
With the X80070, there is some control of the gate current
with the IGQ pins, so one selection of C2 can cover a wide
range of possible loading conditions. Typical values for C2
range from 2.2 to 4.7nF.
When power is applied to the system, the FET tries to turn on
due to its internal gate to drain capacitance (Cgd) and the
feedback capacitor C2 (see Figure 11.) The X80070 device,
when powered, pulls the gate output low to prevent the gate
voltage from rising and keep the FET from turning on. However,
unless V_DD powers up very quickly, there will be a brief period
of time during initial application of power when the X80070
circuits cannot hold the gate low. The use of an external
capacitor (C1) prevents this. Capacitors C1 and C2 form a
voltage divider to prevent the gate voltage from rising above the
FET turn on threshold before the X80070 can hold the gate low.
Use the following formula for choosing C1.
C1 = ^{V-----1-----–}----V-----2- C2
V2
Where:
V1 = Maximum input voltage,
V2 = FET threshold Voltage,
C1 = Gate capacitor,
C2 = Feedback capacitor.
In a system where V_DD rises very fast, a smaller value of C1
may suffice as the X80070 will control voltage at the gate
before the voltage can rise to the FET turn on threshold. The
circuit of Figure 11 assumes that the input voltage can rise to
80V before the X80070 sees operational voltage on V_DD. If C1
is used then the series resistor R1 will be required to revent
high frequency oscillations.
Power Good Indication
The PWRGD signal asserts (Logic LOW) only when all of the
below conditions are true:
– there is no overvoltage or no undervoltage condition, (i.e.
undervoltage < V_EE < overvoltage.)
– There is no overcurrent condition (i.e. V_EE - V_SENSE <
V_OC.)
– The FET is turned on (i.e. V_GATE > V_DD - 1V)
12
FN8150.0
March 15, 2005