ISL78600 Datasheet, PDF (12/22 Pages) Intersil Corporation – Multi-Cell Li-Ion Battery Manager

ISL78600
Electrical Specifications V_BAT = 6 to 60V, T_A = -20°C to +60°C, unless otherwise specified. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 7)
MAX
TYP (Note 7) UNITS
High Level Input Voltage
VIH
1.75
V
Input Hysteresis
VHYS (Note 9)
100
mV
Input Current
Input Capacitance (Note 9)
IIN
0V < V_IN < V3P3
CIN
-1
+1
µA
10
pF
LOGIC INPUTS: EN, COMMS SELECT1, COMMS SELECT2, COMMS RATE 0, COMMS RATE 1
Low Level Input Voltage
VIL
0.3*V3P3 V
High Level Input Voltage
VIH
0.7*V3P3
V
Input Hysteresis
VHYS (Note 9)
0.05*V3P3
V
Input Current
Input Capacitance (Note 9)
IIN
0V < V_IN < V3P3
CIN
-1
+1
µA
10
pF
LOGIC OUTPUTS: DOUT, FAULT, DATA READY
Low Level Output Voltage
VOL1 At 3mA sink current
0
0.4
V
VOL2 At 6mA sink current
0
0.6
V
High Level Output Voltage
VOH1 At 3mA source current
V3P3 – 0.4
V3P3
V
VOH2 At 6mA source current
V3P3 – 0.6
V3P3
V
SPI INTERFACE TIMING - See Figures 1 and 2.
SCLK Clock Frequency
Pulse Width of Input Spikes Suppressed
Enable Lead Time
Clock High Time
Clock Low Time
Enable Lag Time
CHIP SELECT High Time
Slave Access Time
Data Valid Time
Data Output Hold Time (Note 9)
DOUT Disable Time
Data Setup Time
Data Input Hold Time
DATA READY Start Delay Time
DATA READY Stop Delay Time
DATA READY High Time
SPI Communications Timeout
f_SCLK
t_IN1
50
t_LEAD Chip select low to ready to receive clock data
200
t_HIGH (Note 9)
200
t_LOW (Note 9)
200
t_LAG Last data read clock edge to Chip Select high (Note 9)
250
t_CS:WAIT Minimum high time for CS between bytes
200
t_A
Chip Select low to DOUT active. (Note 9)
t_V
Clock low to DOUT valid
t_HO Data hold time after falling edge of SCLK
0
t_DIS DOUT disabled following rising edge of CS (Note 9)
t_SU Data input valid prior to rising edge of SCLK
100
t_HI
Data input to remain valid following rising edge of SCLK
80
t_DR:ST Chip select high to DATA READY low. (Note 9)
100
t_DR:SP Chip select high to DATA READY high. (Note 9)
t_DR:WAIT Time between bytes. (Note 9)
0.6
t_SPI:TO Time the CS remains high before SPI communications
time out - requiring the start of a new command
2
MHz
200
ns
ns
ns
ns
ns
ns
200
ns
350
ns
ns
240
ns
ns
ns
ns
750
ns
µs
100
µs
DOUT Rise Time
DOUT Fall Time
t_R
Up to 50pF load
t_F
Up to 50pF load
30
ns
30
ns
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FN7672.6
January 20, 2015