ISL78600 Datasheet, PDF (11/22 Pages) Intersil Corporation – Multi-Cell Li-Ion Battery Manager

ISL78600
Electrical Specifications V_BAT = 6 to 60V, T_A = -20°C to +60°C, unless otherwise specified. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 7)
Primary Detection Threshold, VC2 to VC12 V_{VC2_12P} V(VC(n - 1))-V(VCn), n = 2 to 12
-2
V_BAT = 39.6V (Note 9)
Secondary Detection Threshold, VC2 to
V_{VC2_12S} Via ADC. VC2 to VC12 only
-100
VC12
V_BAT = 39.6V (Note 9)
Open V_BAT Fault Detection Threshold
V_VBO VC12 - V_BAT
Open VSS Fault Detection Threshold
V_VSSO VSS - VC0
MEASUREMENT FUNCTION TIMING (Note 8)
Cell Sample Time Start
Time to sample the first cell (CELL12) following CS
going High. Scan voltages command
Cell Sample Time Duration
Scan Voltages Processing Time
Scan Temperatures Processing Time
Scan Mixed Processing Time
Scan Wires Processing Time
Scan All Processing Time
Time to scan all 12 cells
(sample of CELL12 to sample of CELL1) scan voltages
command.
Time from start of scan to registers loaded to DATA
READY going low
Time from start of scan to registers loaded to DATA
READY going low
Time from start of scan to registers loaded to DATA
READY going low
Time from start of scan to registers loaded to DATA
READY going low
Time from start of scan to registers loaded to DATA
READY going low
Measure Cell Voltage Processing Time
Time from start of measurement to register(s) loaded
to DATA READY going low
Measure V_BAT Voltage Processing Time
Time from start of measurement to register(s) loaded
to DATA READY going low
Measure Internal Temperature Processing
Time
Time from start of measurement to register(s) loaded
to DATA READY going low
Measure External Temperature Input
Processing Time
Time from start of measurement to register(s) loaded
to DATA READY going low
Measure Secondary Voltage Reference
Time
Time from start of measurement to register(s) loaded
to DATA READY going low
CELL BALANCE OUTPUT SPECIFICATIONS
Cell Balance Pin Output Impedance
R_CBL CBn output off impedance
3
between CB(n) to VC(n-1): cells 1 to 9, and
between CB(n) to VC(n): cells 10 to 12
Cell Balance Output Current
I_CBH1 CBn output on. (CB1-CB9); V_BAT = 39.6V;
-28
device sinking current
I_CBH2 CBn output on. (CB10-CB12); V_BAT = 39.6V;
21
device sourcing current
Cell Balance Output Leakage in Shutdown
I_CBSD EN = GND. V_BAT = 39.6V
-500
External Cell Balance FET Gate Voltage
VGS CBn Output on;
7.04
External 320kΩ between VCn and CBn
(n = 10 to 12) and between CBn and VCn-1
(n = 1 to 9)
Internal Cell Balance Output Clamp
VCBCL I_CB = 100µA
8.94
LOGIC INPUTS: SCLK, CS, DIN
Low Level Input Voltage
VIL
MAX
TYP (Note 7) UNITS
-1.5
0
V
-30
50
mV
200
mV
250
mV
65
71.5
µs
233 257
µs
770 847
µs
2690 2959
µs
830 913
µs
59.4 65.3
ms
63.2 69.5
ms
180 198
µs
130 143
µs
110 121
µs
2520 2772
µs
2520 2772
µs
4
5
MΩ
-25
-21
μA
25
28
μA
10
700
nA
8.0 8.96
V
V
0.8
V
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FN7672.6
January 20, 2015