ISL78310_15 Datasheet, PDF (12/14 Pages) Intersil Corporation – High Performance 1A LDO

ISL78310
Power Dissipation
The junction temperature must not exceed the range specified in
the “Recommended Operating Conditions” on page 5. The power
dissipation can be calculated by using Equation 6:
P_D = V_IN – V_OUT  I_OUT + V_IN  I_GND
(EQ. 6)
The maximum allowed junction temperature, T_J(MAX), and the
maximum expected ambient temperature, T_A(MAX), will
determine the maximum allowable power dissipation, as shown
in Equation 7:
P_{DMAX} = T_{JMAX} – T_A  _JA
(EQ. 7)
_JA is the junction-to-ambient thermal resistance.
For safe operation, ensure that the power dissipation P_D,
calculated from Equation 6, is less than the maximum allowable
power dissipation P_D(MAX).
Heatsinking the DFN Package
The DFN package uses the copper area on the PCB as a heat-sink.
The EPAD of this package must be soldered to the copper plane
(GND plane) for heat sinking. Figure 17 shows a curve for the _JA
of the DFN package for different copper area sizes.
46
44
42
40
38
36
34
2 4 6 8 10 12 14 16 18 20 22 24
EPAD-MOUNT COPPER LAND AREA ON PCB, mm²
FIGURE 17. 3mmx3mm 10 LD DFN ON 4-LAYER PCB WITH THERMAL
VIAS _JA vs EPAD-MOUNT COPPER LAND AREA ON PCB
General Power PAD Design
Considerations
Figure 18 shows the recommended use of vias on the thermal
pad to remove heat from the IC. This typical array populates the
thermal pad footprint with vias spaced three times the radius
distance from the center of each via. Small via size is advisable,
but not to the extent that solder reflow becomes difficult.
All vias should be connected to the pad potential, with low
thermal resistance for efficient heat transfer. Complete
connection of the plated-through hole to each plane is important.
It is not recommended to use “thermal relief” patterns to connect
the vias.
FIGURE 18. PCB VIA PATTERN
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FN7810.2
November 7, 2014