ISL6753_14 Datasheet, PDF (12/15 Pages) Intersil Corporation – ZVS Full-Bridge PWM Controller

ISL6753
If the application requires deadtime less than about 500ns,
the CTBUF signal may not perform adequately for slope
compensation. CTBUF lags the CT sawtooth waveform by
300-400ns. This behavior results in a non-zero value of
CTBUF when the next half-cycle begins when the deadtime
is short.
Under these situations, slope compensation may be added
by externally buffering the CT signal as shown below.
1
VREF 16
2
15
3
ISL6753
14
4
13
5 CT
12
6
11
R9
7
10
8 CS
9
R6
R_CS
C4
CT
FIGURE 8. ADDING SLOPE COMPENSATION USING CT
Using CT to provide slope compensation instead of CTBUF
requires the same calculations, except that Equations 21
and 22 require modification. Equation 21 becomes:
V_e – ∆V_CS
=
-²----^D------^â‹---^R-----⁶---
R6 + R9
V
(EQ. 25)
and Equation 22 becomes:
R9 = -⁽--²----^D------^–----^V----^e-----⁺-----^∆----^V----^C----^S----⁾----^â‹---^R----⁶--
Ω
V_e – ∆V_CS
(EQ. 26)
The buffer transistor used to create the external ramp from
CT should have a sufficiently high gain so as to minimize the
required base current. Whatever base current is required
reduces the charging current into CT and will reduce the
oscillator frequency.
ZVS Full-Bridge Operation
The ISL6753 is a full-bridge zero-voltage switching (ZVS)
PWM controller that behaves much like a traditional hard-
switched topology controller. Rather than drive the diagonal
bridge switches simultaneously, the upper switches (OUTUL,
OUTUR) are driven at a fixed 50% duty cycle and the lower
switches (OUTLL, OUTLR) are pulse width modulated on
the trailing edge.
CT
DEADTIME
OUTLL
OUTLR
PWM
PWM
PWM
PWM
OUTUR
RESONANT
DELAY
OUTUL
RESDEL
WINDOW
FIGURE 9. BRIDGE DRIVE SIGNAL TIMING
To understand how the ZVS method operates one must
include the parasitic elements of the circuit and examine a
full switching cycle.
VIN+
UL
UR
D1
L_L
VOUT+
RTN
LL
LR
D2
VIN-
FIGURE 10. IDEALIZED FULL-BRIDGE
In Figure 10, the power semiconductor switches have been
replaced by ideal switch elements with parallel diodes and
capacitance, the output rectifiers are ideal, and the
transformer leakage inductance has been included as a
discrete element. The parasitic capacitance has been
lumped together as switch capacitance, but represents all
parasitic capacitance in the circuit including winding
capacitance. Each switch is designated by its position, upper
left (UL), upper right (UR), lower left (LL), and lower right
(LR). The beginning of the cycle, shown in Figure 11, is
arbitrarily set as having switches UL and LR on and UR and
LL off. The direction of the primary and secondary currents
are indicated by I_P and I_S, respectively.
12
FN9182.2
April 4, 2006