ISL6526 Datasheet, PDF (12/15 Pages) Intersil Corporation – Single Synchronous Buck Pulse-Width Modulation PWM Controller

ISL6526, ISL6526A
input voltage and a voltage rating of 1.5 times is a
conservative guideline. The RMS current rating requirement
for the input capacitor of a buck regulator is approximately
1/2 the DC load current.
The maximum RMS current required by the regulator may be
closely approximated using Equation 15:
I_RMSMAX =
V_{-----O----U---T-}
V_IN
×
⎛
⎝
I_O
UTM
A
2
X
+
--¹----
12
×
⎛
⎝
-^V----^I-^N-----–-----^V----^O----^U---^T-
L × f_s
×
V_{---V--O--I--UN---T-⎠⎞}
2_⎞
⎠
(EQ. 15)
For a through hole design, several electrolytic capacitors may
be needed. For surface mount designs, solid tantalum
capacitors can be used, but caution must be exercised with
regard to the capacitor surge current rating. These capacitors
must be capable of handling the surge-current at power-up.
Some capacitor series available from reputable manufacturers
are surge current tested.
MOSFET Selection/Considerations
The ISL6526, ISL6526A require two N-Channel power
MOSFETs. These should be selected based upon r_DS(ON),
gate supply requirements, and thermal management
requirements.
In high-current applications, the MOSFET power dissipation,
package selection and heatsink are the dominant design
factors. The power dissipation includes two loss components;
conduction loss and switching loss. The conduction losses are
the largest component of power dissipation for both the upper
and the lower MOSFETs. These losses are distributed
between the two MOSFETs according to duty factor. The
switching losses seen when sourcing current will be different
from the switching losses seen when sinking current. When
sourcing current, the upper MOSFET realizes most of the
switching losses. The lower switch realizes most of the
switching losses when the converter is sinking current (see
Equations 16 and 17). These equations assume linear
voltage-current transitions and do not adequately model
power loss due the reverse-recovery of the upper and lower
MOSFET’s body diode. The gate-charge losses are
dissipated by the ISL6526, ISL6526A and don't heat the
MOSFETs. However, large gate-charge increases the
switching interval, t_SW which increases the MOSFET
switching losses. Ensure that both MOSFETs are within their
maximum junction temperature at high ambient temperature
by calculating the temperature rise according to package
thermal-resistance specifications. A separate heatsink may be
necessary depending upon MOSFET power, package type,
ambient temperature and air flow.
Losses while Sourcing Current
P_UPPER
=
I
o²
×
r_DS(O
N)
×
D
+
1_--
2
⋅
I
o
×
V_I
N
×
t_S
W
×
f_s
P_LOWER = Io² x r_DS(ON) x (1 - D)
(EQ. 16)
Losses while Sinking Current
P_UPPER = Io² x r_DS(ON) x D
P_LOWER
=
Io²
×
r_D
S
(
O
N
)
×
(
1
–
D)
+
1_--
2
⋅
I
o
×
V_IN
×
t_SW
×
f_s
Where: D is the duty cycle = V_OUT/V_IN,
t_SW is the combined switch ON and OFF time, and
f_s is the switching frequency.
(EQ. 17)
Given the reduced available gate bias voltage (5V), logic-level
or sub-logic-level transistors should be used for both
N-MOSFETs. Caution should be exercised with devices
exhibiting very low V_GS(ON) characteristics. The shoot-through
protection present aboard the ISL6526, ISL6526A may be
circumvented by these MOSFETs if they have large parasitic
impedances and/or capacitances that would inhibit the gate of
the MOSFET from being discharged below its threshold level
before the complementary MOSFET is turned on.
Bootstrap Component Selection
External bootstrap components, a diode and capacitor, are
required to provide sufficient gate enhancement to the upper
MOSFET. The internal MOSFET gate driver is supplied by the
external bootstrap circuitry, as shown in Figure 7. The boot
capacitor, C_BOOT, develops a floating supply voltage
referenced to the PHASE pin. This supply is refreshed each
cycle, when D_BOOT conducts, to a voltage of CPVOUT less the
boot diode drop, V_D, plus the voltage rise across Q_LOWER.
ISL6526,
ISL6526A
CPVOUT
D_{BOOT +}
V_D
V_IN
-
BOOT
C_BOOT
UGATE
PHASE
Q_UPPER
NOTE:
V_G-S = V_CC -V_D
-
LGATE
Q_LOWER
+
GND
NOTE:
V_G-S = V_CC
FIGURE 7. UPPER GATE DRIVE BOOTSTRAP
Just after the PWM switching cycle begins and the charge
transfer from the bootstrap capacitor to the gate capacitance
is complete, the voltage on the bootstrap capacitor is at its
lowest point during the switching cycle. The charge lost on
the bootstrap capacitor will be equal to the charge
transferred to the equivalent gate-source capacitance of the
upper MOSFET as shown in Equation 18:
Q_GATE = C_BOOT × (V_BOOT1 – V_BOOT2)
(EQ. 18)
12
FN9055.10
November 24, 2008