ISL6526 Datasheet, PDF (10/15 Pages) Intersil Corporation – Single Synchronous Buck Pulse-Width Modulation PWM Controller

ISL6526, ISL6526A
the PHASE node. The PWM wave is smoothed by the output
filter (L_O and C_O).
The modulator transfer function is the small-signal transfer
function of V_OUT/V_E/A. This function is dominated by a DC
Gain and the output filter (L_O and C_O), with a double pole
break frequency at f_LC and a zero at f_ESR. The DC Gain of
the modulator is simply the input voltage (V_IN) divided by the
peak-to-peak oscillator voltage ΔV_OSC.
OSC
PWM
COMPARATOR
-
Δ V_OSC
+
DRIVER
DRIVER
V_IN
L_O
PHASE _CO
V_OUT
Z_FB
V_E/A
-
Z_IN
+
ERROR ^REFERENCE
AMP
ESR
(PARASITIC)
DETAILED COMPENSATION COMPONENTS
C₁
C₂
R₂
Z_FB
V_OUT
Z_IN
C₃ R₃
COMP
-
+
R₁
FB
ISL6526, ISL6526A
REFERENCE
FIGURE 5. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
Modulator Break Frequency Equations
f_LC=
--------------------¹---------------------
2π x L_O x C_O
(EQ. 4)
f_ESR=
---------------------¹---------------------
2π x ESR x C_O
(EQ. 5)
The compensation network consists of the error amplifier
(internal to the ISL6526, ISL6526A) and the impedance
networks Z_IN and Z_FB. The goal of the compensation
network is to provide a closed loop transfer function with the
highest 0dB crossing frequency (f_0dB) and adequate phase
margin. Phase margin is the difference between the closed
loop phase at f_0dB and 180°. Equations 6, 7, 8 and 9 relate
the compensation network’s poles, zeros and gain to the
components (R₁, R₂, R₃, C₁, C₂, and C₃) in Figure 5. Use
these guidelines for locating the poles and zeros of the
compensation network:
1. Pick gain (R₂/R₁) for desired converter bandwidth.
10
2. Place first zero below filter’s double pole (~75% f_LC).
3. Place second zero at filter’s double pole.
4. Place first pole at the ESR zero.
5. Place second pole at half the switching frequency.
6. Check gain against error amplifier’s open-loop gain.
7. Estimate phase margin - repeat if necessary.
Compensation Break Frequency Equations
f_Z1
=
----------------¹------------------
2π × R₂ × C₂
(EQ. 6)
f_Z2
=
---------------------------¹---------------------------
2π x (R₁ + R₃) x C₃
(EQ. 7)
f_P1
=
---------------------------¹-----------------------------
2π
x
R₂
x
⎛
⎜
⎝
C_{-C----1-1----+}x_{-----CC----2-2-⎠⎟⎞}
f_P2
=
-----------------¹------------------
2π x R₃ x C₃
(EQ. 8)
(EQ. 9)
Figure 6 shows an asymptotic plot of the DC/DC converter’s
gain vs frequency. The actual Modulator Gain has a high gain
peak due to the high Q factor of the output filter and is not
shown in Figure 6. Using the previously mentioned guidelines
should give a Compensation Gain similar to the curve plotted.
The open loop error amplifier gain bounds the compensation
gain. Check the compensation gain at f_P2 with the capabilities
of the error amplifier. The Closed Loop Gain is constructed on
the graph of Figure 6 by adding the Modulator Gain (in dB) to
the Compensation Gain (in dB). This is equivalent to
multiplying the modulator transfer function to the
compensation transfer function and plotting the gain.
The compensation gain uses external impedance networks
Z_FB and Z_IN to provide a stable, high bandwidth (BW) overall
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than
45°. Include worst case component variations when
determining phase margin.
f_Z1
f_Z2
f_P1 f_P2
OPEN LOOP
100
ERROR AMP GAIN
80
20 log
⎛
⎜
⎝
V^----V-_O^----I-_S^-N---_C^---_{⎠⎟⎞}
60
40
COMPENSATION
GAIN
20
0
-20
20 log _⎝⎛ ^RR-----²¹--_⎠⎞
MODULATOR
-40
GAIN
f_LC f_ESR
LOOP GAIN
-60
10
100
1k
10k 100k 1M 10M
FREQUENCY (Hz)
FIGURE 6. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
FN9055.10
November 24, 2008