ISL6444 Datasheet, PDF (12/18 Pages) Intersil Corporation – Dual PWM Controller with DDR Memory Option for Gateway Applications

ISL6444
In the case when power for VDDQ is taken from the +5V
system rail, as Figure 8 shows, both in-phase and out-of-
phase approaches are susceptible to noise in the sourcing
mode.
300kHz CLOCK
VDDQ
Noise immunity can be improved by operating the VTT
converter with a 90^o phase shift. As the time diagrams in
Figure 8 show, the points of concern are always about a
quarter of the period away from the noise emitting
transitions.
300kHz CLOCK
VDDQ
SOURCING
VTT
OUT-OF-PHASE
SINKING
SOURCING
VTT
IN-PHASE
SINKING
FIGURE 7. CHANNEL INTRFEARENCE Vin=7.5V...24V
SOURCING
VTT
SINKING
SOURCING
VTT
SINKING
SOURCING
VTT
OUT-OF-PHASE
IN-PHASE
90^o PHASE SHIFT
SINKING
FIGURE 8. CHANNEL INTERFERENCE Vin=5V
Several ways of synchronization are implemented into the
chip. When the DDR pin is connected to GND, the channels
operate 180^o out-of-phase. In the DDR mode when the DDR
pin is connected to VCC, the channels operate either in-
phase when the VIN pin is connected to the input voltage
source, or with 90^o phase shift if the VIN pin is connected to
GND via the 100kOhm resistor.
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