ISL6422B_15 Datasheet, PDF (12/19 Pages) Intersil Corporation – Dual Output LNB Supply and Control Voltage Regulator with I2C Interface for Advanced Satellite Set-Top Box Designs

ISL6422B
The STOP condition is a LOW to HIGH transition on the SDA
line while SCL is HIGH. A STOP condition must be sent
before each START condition.
SDA
SCL
S
P
START
CONDITION
STOP
CONDITION
FIGURE 5. START AND STOP WAVEFORMS
Byte Format
Every byte put on the SDA line must be eight bits long. The
number of bytes that can be transmitted per transfer is
unrestricted. Each byte has to be followed by an
acknowledge bit. Data is transferred with the most significant
bit first (MSB).
Acknowledge
The master (microprocessor) puts a resistive HIGH level on
the SDA line during the acknowledge clock pulse (Figure 6).
The peripheral that acknowledges has to pull-down (LOW)
the SDA line during the acknowledge clock pulse so that the
SDA line is stable LOW during this clock pulse (of course,
set-up and hold times must also be taken into account).
The peripheral which has been addressed has to generate
an acknowledge after the reception of each byte, otherwise
the SDA line remains at the HIGH level during the ninth
clock pulse time. In this case, the master transmitter can
generate the STOP information in order to abort the transfer.
The ISL6422B will not generate the acknowledge if the
POWER OK signal from the UVLO is LOW.
SCL
1
2
8
9
SDA
START
MSB
ACKNOWLEDGE
FROM SLAVE
FIGURE 6. ACKNOWLEDGE ON THE I²C BUS
Transmission Without Acknowledge
Avoiding detection of the acknowledgement, the
microprocessor can use a simpler transmission; it waits one
clock without checking the slave acknowledging, and sends
the new data. Although, this approach is less protected from
error and decreases the noise immunity.
ISL6422B Software Description
Interface Protocol
The interface protocol is comprised of the following, as
shown below in Table 2:
• A start condition (S)
• A chip address byte (MSB on left; the LSB bit determines
read (1) or write (0) transmission) (the assigned I²C slave
address for the ISL6422B is 0001 00XX)
• A sequence of data (1 byte + Acknowledge)
• A stop condition (P)
TABLE 2. INTERFACE PROTOCOL
S 0 0 0 1 0 0 0 R/W ACK Data (8 bits)
ACK P
System Register Format
• R, W = Read and Write bit
• R = Read-only bit
All bits reset to 0 at Power-On
TABLE 3. STATUS REGISTER 1 (SR1)
R, W R, W R, W R
R
R
R
R
SR1H SR1M SR1L OTF CABF1 OUVF1 OLF1 BCF1
TABLE 4. TONE REGISTER 2 (SR2)
R, W R, W R, W R, W R, W R, W R, W
SR2H SR2M SR2L ENT1 MSEL1 TTH1 X
R, W
X
TABLE 5. COMMAND REGISTER 3 (SR3)
R, W R, W R, W R, W R, W R, W R, W R, W
SR3H SR3M SR3L DCL1 VSPEN1 ISEL1R ISEL1H ISEL1L
TABLE 6. CONTROL REGISTER 4 (SR4)
R, W R, W R, W R, W R, W R, W R, W R, W
SR4H SR4M SR4L EN1 X
X VTOP1 VBOT1
TABLE 7. STATUS REGISTER 5 (SR5)
R, W R, W R, W X
R
R
R
R
SR5H SR5M SR5L X CABF2 OUVF2 OLF2 BCF2
TABLE 8. TONE REGISTER 6 (SR6)
R, W R, W R, W R, W R, W R, W R, W
SR6H SR6M SR6L ENT2 MSEL2 TTH2 X
R, W
X
TABLE 9. COMMAND REGISTER 7 (SR7)
R, W R, W R, W R, W R, W R, W R, W R, W
SR7H SR7M SR7L DCL2 VSPEN2 ISEL2R ISEL2H ISEL2L
TABLE 10. CONTROL REGISTER 8 (SR8)
R, W R, W R, W R, W R, W R, W R, W R, W
SR8H SR8M SR8L EN2 X
X VTOP2 VBOT2
NOTE: X = Bit not used
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FN6486.2
September 8, 2015