ISL6269AIRZ-T Datasheet, PDF (12/14 Pages) Intersil Corporation – High-Performance Notebook PWM Controller

ISL6269A
high-side MOSFET emphasizes low switch charge so that
the device spends the least amount of time dissipating
power in the linear region. Unlike the low-side MOSFET
which has the drain-source voltage clamped by its body
diode during turn off, the high-side MOSFET turns off with
V_IN - V_OUT - V_Lacross it. The preferred low-side MOSFET
emphasizes low r_DS(ON) when fully saturated to minimize
conduction loss.
For the low-side MOSFET, (LS), the power loss can be
assumed to be conductive only and is written as:
P_{CON_LS} ≈ I_LOAD2 ⋅ r_{DS(ON)_LS} • (1 – D)
(EQ. 16)
For the high-side MOSFET, (HS), its conduction loss is
written as:
P_{CON_HS} = I_LOAD2 • r_{DS(ON)_HS} • D
(EQ. 17)
For the high-side MOSFET, its switching loss is written as:
P_{SW_HS}
=
-^V----^I--^N----^•---^I--^V----^A----^L---^L---^E----^Y-----^•--^t--^O-----^N----^•---^f--^S----^W---
2
+
-^V----^I--^N----^•---^I--^P----^E----^A----^K----^•---^t--^O----^F----^F----^•---^f-^S----^W----
2
(EQ. 18)
Where:
- I_VALLEY is the difference of the DC component of the
inductor current minus 1/2 of the inductor ripple current
- I_PEAK is the sum of the DC component of the inductor
current plus 1/2 of the inductor ripple current
- t_ON is the time required to drive the device into
saturation
- t_OFF is the time required to drive the device into cut-off
Selecting The Bootstrap Capacitor
The selection of the bootstrap capacitor is written as:
C_BOOT
=
---------^Q-----^g---------
ΔV_BOOT
(EQ. 19)
Where:
- Q_g is the total gate charge required to turn on the
high-side MOSFET
- ΔV_BOOT, is the maximum allowed voltage decay across
the boot capacitor each time the high-side MOSFET is
switched on
As an example, suppose the high-side MOSFET has a total
gate charge Q_g, of 25nC at V_GS = 5V, and a ΔV_BOOT of
200mV. The calculated bootstrap capacitance is 0.125µF; for
a comfortable margin select a capacitor that is double the
calculated capacitance, in this example 0.22µF will suffice.
Use an X7R or X5R ceramic capacitor.
Layout Considerations
As a general rule, power should be on the bottom layer of
the PCB and weak analog or logic signals are on the top
layer of the PCB. The ground-plane layer should be adjacent
to the top layer to provide shielding. The ground plane layer
should have an island located under the IC, the compensation
components, and the FSET components. The island should be
connected to the rest of the ground plane layer at one point.
VIAS TO
GROUND
PLANE
INDUCTOR
HIGH-SIDE
MOSFETS
GND
VOUT
OUTPUT
CAPACITORS
SCHOTTKY
DIODE
PHASE
NODE
LOW-SIDE
MOSFETS
INPUT
VIN
CAPACITORS
FIGURE 8. TYPICAL POWER COMPONENT PLACEMENT
Signal Ground and Power Ground
The bottom of the ISL6269A QFN package is the signal
ground (GND) terminal for analog and logic signals of the IC.
Connect the GND pad of the ISL6269A to the island of
ground plane under the top layer using several vias, for a
robust thermal and electrical conduction path. Connect the
input capacitors, the output capacitors, and the source of the
lower MOSFETs to the power ground plane.
PGND (Pin 10)
This is the return path for the pull-down of the LG low-side
MOSFET gate driver. Ideally, PGND should be connected to
the source of the low-side MOSFET with a low-resistance,
low-inductance path .
VIN (Pin 1)
The VIN pin should be connected close to the drain of the
high-side MOSFET, using a low resistance and low
inductance path.
VCC (Pin 2)
For best performance, place the decoupling capacitor very
close to the VCC and GND pins.
PVCC (Pin 12)
For best performance, place the decoupling capacitor very
close to the PVCC and PGND pins, preferably on the same
side of the PCB as the ISL6269A IC.
FCCM (Pin 3), EN (Pin 4), and PGOOD (Pin 16)
These are logic inputs that are referenced to the GND pin.
Treat as a typical logic signal.
COMP (Pin 5), FB (Pin 6), and VO (Pin 8)
For best results, use an isolated sense line from the output
load to the VO pin. The input impedance of the FB pin is
high, so place the voltage programming and loop
compensation components close to the VO, FB, and GND
pins keeping the high impedance trace short.
FSET (Pin 7)
This pin requires a quiet environment. The resistor R_FSET
and capacitor C_FSET should be placed directly adjacent to
this pin. Keep fast moving nodes away from this pin.
12
FN9253.2
May 30, 2007