ISL6263B Datasheet, PDF (12/18 Pages) Intersil Corporation – 5-Bit VID Single-Phase Voltage Regulator with Current Monitor for IMVP-6+ Santa Rosa GPU Core

ISL6263B
ISL6263B will latch UGATE and PGOOD low but unlike other
protective faults, LGATE remains high until the voltage
between VO and VSS falls below approximately 0.77V, at
which time LGATE is pulled low. The LGATE pin will continue
to switch high and low at 1.545V and 0.77V until VDD has
gone below the falling POR threshold voltage ^V_{VDD_THF.}
This provides maximum protection against a shorted
high-side MOSFET while preventing the output voltage from
ringing below ground. The severe-overvoltage fault circuit
can be triggered after another fault has already been
latched.
TABLE 3. FAULT PROTECTION SUMMARY OF ISL6263B
FAULT TYPE
FAULT
DURATION
PRIOR TO
PROTECTION
PROTECTION
ACTIONS
FAULT
RESET
Overcurrent
120µs
LGATE, UGATE, and Cycle
PGOOD latched low VR_ON or
VDD
Short Circuit
<2µs
LGATE, UGATE, and Cycle
PGOOD latched low VR_ON or
VDD
Overvoltage
(+195mV)
between VO pin
and SOFT pin
1ms
LGATE, UGATE, and Cycle
PGOOD latched low VR_ON or
VDD
Severe
Overvoltage
(+1.55V)
between VO pin
and VSS pin
Immediately
UGATE, and
Cycle
PGOOD latched low, VDD only
LGATE toggles ON
when VO>1.55V
OFF when
VO <0.77V
until fault reset
Undervoltage
(-300mV)
between VO pin
and SOFT pin
1ms
LGATE, UGATE, and Cycle
PGOOD latched low VR_ON or
VDD
Gate-Driver Outputs LGATE and UGATE
The ISL6263B has internal high-side and low-side
N-Channel MOSFET gate-drivers. The LGATE driver is
optimized for low duty-cycle applications where the low-side
MOSFET conduction losses are dominant. The LGATE
pull-down resistance is very low in order to clamp the
gate-source voltage of the MOSFET below the V_GS(th) at
turnoff. The current transient through the low-side gate at
turnoff can be considerable due to the characteristic large
switching charge of a low r_DS(ON) MOSFET.
PWM
LGATE
1V
UGATE
1V
t _PDRU
t _PDRL
FIGURE 6. GATE DRIVER TIMING DIAGRAM
Adaptive shoot-through protection prevents the gate-driver
outputs from going high until the opposite gate-driver output
has fallen below approximately 1V. The UGATE turn-on
propagation delay t_PDRU and LGATE turn-on propagation
delay t_PDRL are found in the “Electrical Specifications” table
on page 6. The power for the LGATE gate-driver is sourced
directly from the PVCC pin. The power for the UGATE
gate-driver is sourced from a boot-strap capacitor connected
across the BOOT and PHASE pins. The boot capacitor is
charged from PVCC through an internal boot-strap diode
each time the low-side MOSFET turns on, pulling the
PHASE pin low.
Internal Bootstrap Diode
The ISL6263B has an integrated boot-strap Schottky diode
connected from the PVCC pin to the BOOT pin. Simply
adding an external capacitor across the BOOT and PHASE
pins completes the bootstrap circuit.
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
Q_GATE = 100nC
0.4
0.2 _20nC
0.0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
ΔV_{BOOT_CAP} (V)
FIGURE 7. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE
VOLTAGE
12
FN6388.3
July 8, 2010