ISL6174_14 Datasheet, PDF (12/16 Pages) Intersil Corporation – Dual Low Voltage Circuit Breaker

ISL6174
Pins SS1 and SS2 of the IC are available as jumper test
points so that they can be tied together to achieve
concurrent tracking between Vo1 and Vo2. Both the EN
inputs must be turned on together to check this function,
jumpers are provide to facilitate this.
Each channel is preloaded with the resistive load that makes
up the UV threshold level. Additional loading can be
externally applied as desired.
The internal Circuit Breaker amplifier is fast enough to
respond to very fast di/dt events.
On this board, the timeout capacitor value for side ‘1’ is
0.15µF, which corresponds to a timeout period of 17.67ms.
The scope shots are taken from the ISL6174EVAL1 to
demonstrate the ISL6174s critical operational waveforms.
Figure 18 illustrates the circuit breaker operation which will
be evident with a slow ramping output current at the
programmed 2.2A level, I_CB. This mode of operation will be
invoked while the OC event is < ~2X the I_CB. as shown in
Figure 19. Characteristic of this operational mode is the TCB
pin ramping to V_CB to establish the circuit breaker delay.
GATE
GATE
Iin
TCB
FIGURE 19. TRANSIENT TO 3.9A OC CIRCUIT BREAKER
OPERATION
The way to confirm WOC mode, is by looking at the TCB pin
waveform. If no ramping is seen prior to GATE turn off, then
WOC is active. The following waveform in Figure 20 shows
WOC operation:
:
GATE
TCB
Iin
TCB
Iin
FIGURE 18. SLOW RAMPING TO 2.2A OC CIRCUIT BREAKER
OPERATION
FIGURE 20. WOC CIRCUIT BREAKER OPERATION
Figure 21 is a 200X zoom of a WOC turn-off event and
clearly illustrates the lack of any TCB ramping during this
WOC event.
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FN6830.0
December 19, 2008