ISL6174_14 Datasheet, PDF (10/16 Pages) Intersil Corporation – Dual Low Voltage Circuit Breaker

ISL6174
I_o
V_IN
+
-
V_O
+
Rsns
Q
I_SET R_SET
-
ISL6174
3k
OC COMPARATOR
-
+
GATE
PULLDOWN
CURRENT
-
+
WOC
25Ω
COMPARATOR
FIGURE 16. OC / WOC OPERATION
Bias and Charge Pump Voltages:
The BIAS pin feeds the chip bias voltage directly to the first
of the two internal charge pumps, which are cascaded. The
output of the first charge pump, in addition to feeding the
second charge pump, is accessible on the CPVDD pin. The
voltage on the CPVDD pin is approximately 5V. It also
provides power to the POR and band-gap circuitry as shown
in the block diagram. A capacitor connected externally
across CPQ+ and CPQ- pins of the IC is the “flying” cap for
the charge-pump.
The second charge-pump is used exclusively to drive the
gates of the MOSFETs during soft start through the 24µA
current sources, one for each channel. The output of this
charge pump is approximately 10V as shown in the “Block
Diagram” on page 2.
Typical Hot-plug Power Up Sequence
1. When power is applied to the IC on the BIAS pin, the first
charge pump immediately powers up.
2. If the BIAS voltage is 2.1V or higher, the IC comes out of
POR. Both SS and TCB caps remain discharged and the
gate (GT) voltage remains low.
3. ENx pin, when pulled below it’s specified threshold,
enables the respective channel.
4. SSx cap begins to charge up through the internal 10µA
current source, the gate (GT) voltage begins to rise and
the corresponding output voltage begins to rise at the
same rate as the SS cap voltage. This is tightly controlled
by the soft-start amplifier shown in the block diagram.
5. SS cap begins to charge but the corresponding TCBx cap
is held discharged.
6. Fault (FLT) remains deasserted (stays high) and the
output voltage continues to rise.
10
7. If the load current on the output exceeds the set current
limit for greater than the circuit breaker delay, FLT gets
asserted and the channel shutdown occurs.
8. If the voltage on UV pin exceeds 633mV threshold as a
result of rising Vo, the Power Good (PG) output goes
active.
9. At the end of the SS interval, the SS cap voltage reaches
CPVDD and remains charged as long as EN remains
asserted or there is no other fault condition present that
would attempt to pull down the gate.
Applications Information
Selection of External Components
The typical application circuit of Figure 2 has been used for
this section, which provides guidelines to select the external
component values.
MOSFET (Q1)
This component should be selected on the basis of its
r_DS(ON) specification at the expected Vgs (gate to source
voltage) and the effective input gate capacitance (Ciss). One
needs to ensure that the combined voltage drop across the
Rsense and r_DS(ON) at the desired maximum current
(including transients) will still keep the output voltage above
the minimum required level.
Ciss of the MOSFET influences the overcurrent response
time. It is recommended that a MOSFET with Ciss of less
than 10nF be chosen. Ciss will also have an impact on the
SS cap value selection as seen later.
Current Sense Resistor (R_SNS)
The voltage drop across this resistor, which represents the
load current (Io), is compared against the set threshold of
the Circuit Breaker comparator. The value of this resistor is
determined by how much combined voltage drop is tolerable
between the source and the load. It is recommended that at
least 20mV drop be allowed across this resistor at max load
current. This resistor is expected to carry maximum full load
current indefinitely. Hence, the power rating of this resistor
must be greater than I_O(MAX)2*R_SNS.
This resistor is typically a low value resistor and hence the
voltage signal appearing across it is also small. In order to
maintain high current sense accuracy, current sense trace
routing is critical. It is recommended that either a four wire
resistor or the routing method as shown in Figure 17 be
used.
FN6830.0
December 19, 2008