ISL22424 Datasheet, PDF (12/18 Pages) Intersil Corporation – Dual Digitally Controlled Potentiometer (XDCP™)

ISL22424
contains all zeroes (WRi[7:0]= 00h), its wiper terminal (RWi) is
closest to its “Low” terminal (RLi). When the WRi register of a
DCP contains all ones (WRi[7:0]= FFh), its wiper terminal
(RWi) is closest to its “High” terminal (RHi). As the value of the
WRi increases from all zeroes (0) to all ones (255 decimal),
the wiper moves monotonically from the position closest to
RLi to the closest to RHi. At the same time, the resistance
between RWi and RLi increases monotonically, while the
resistance between RHi and RWi decreases monotonically.
While the ISL22424 is being powered up, the WRi is reset to
80h (128 decimal), which locates RWi roughly at the center
between RLi and RHi. After the power supply voltage
becomes large enough for reliable non-volatile memory
reading, the WRi will be reloaded with the value stored in a
corresponding non-volatile Initial Value Register (IVRi).
The WRi and IVRi can be read or written to directly using the
SPI serial interface as described in the following sections.
Memory Description
The ISL22424 contains two non-volatile 8-bit Initial Value
Registers (IVRi), thirteen non-volatile 8-bit General Purpose
(GP) registers, two volatile 8-bit Wiper Registers (WRi), and
volatile 8-bit Access Control Register (ACR). The memory
map of ISL22424 is in Table 1.
TABLE 1. MEMORY MAP
ADDRESS
(hex)
NON-VOLATILE
VOLATILE
10
N/A
ACR
F
Reserved
E
General Purpose
N/A
D
General Purpose
N/A
C
General Purpose
N/A
B
General Purpose
N/A
A
General Purpose
N/A
9
General Purpose
N/A
8
General Purpose
N/A
7
General Purpose
N/A
6
General Purpose
N/A
5
General Purpose
N/A
4
General Purpose
N/A
3
General Purpose
N/A
2
General Purpose
N/A
1
IVR1
WR1
0
IVR0
WR0
The non-volatile registers (IVRi) at address 0 and 1, contain
initial wiper position and volatile registers (WRi) contain
current wiper position.
The register at address 0Fh is a read-only reserved register.
Information read from this register should be ignored.
The non-volatile IVRi and volatile WRi registers are
accessible with the same address.
The Access Control Register (ACR) contains information
and control bits described below in Table 2.
The VOL bit (ACR[7]) determines whether the access to
wiper registers WRi or initial value registers IVRi.
TABLE 2. ACCESS CONTROL REGISTER (ACR)
BIT # 7
6
54
3
2
1
0
BIT VOL SHDN WIP 0
0
0 SDO 0
NAME
If VOL bit is 0, the non-volatile IVRi and General Purpose
registers are accessible. If VOL bit is 1, only the volatile WRi
are accessible. Note: value that is written to IVRi register
also is written to the corresponding WRi. The default value of
this bit is 0.
The SHDN bit (ACR[6]) disables or enables Shutdown
mode. When this bit is 0, DCP is in Shutdown mode, i.e.
each DCP is forced to end-to-end open circuit and RWi is
shorted to RLi as shown on Figure 15. Default value of
SHDN bit is 1.
RHi
RWi
RLi
FIGURE 15. DCP CONNECTION IN SHUTDOWN MODE
Setting SHDN bit to 1 is returned wipers to prior to Shutdown
Mode position.
The WIP bit (ACR[5]) is a read-only bit. It indicates that non-
volatile write operation is in progress. The WIP bit can be
read repeatedly after a non-volatile write to determine if the
write has been completed. It is impossible to write or read to
the WRi or ACR while WIP bit is 1.
The SDO bit (ACR[1]) configures type of SDO output pin.
The default value of SDO bit is 0 for Push - Pull output. SDO
pin can be configured as Open Drain output for some
application. In this case, an external pull up resistor is
required. See “Applications Information” on page 14.
SPI Serial Interface
The ISL22424 supports an SPI serial protocol, mode 0. The
device is accessed via the SDI input and SDO output with
data clocked in on the rising edge of SCK, and clocked out
on the falling edge of SCK. CS must be LOW during
communication with the ISL22424. SCK and CS lines are
12
FN6425.0
May 31, 2007