D2-7XX83 Datasheet, PDF (12/32 Pages) Intersil Corporation – Powered Speaker Systems

D2-7xx83
Pin Descriptions (Continued)
PIN
NAME
PIN (Note 15) TYPE
34 GPIO5
I/O
35 GPIO6
I/O
36 SDA1
I/O
37
SCL1
I/O
38 PROTECT9 I/O
39 SPDIFRX1 I
40 SPDIFRX0 I
41 SPDIFTX O
42
TEST
I
43
IRQA
I
44
IRQB
I
45
IRQC
I
46
IRQD
I
47
TIO2
I/O
48 CVDD
P
49 CVDD
P
50 CGND
P
51 CGND
P
52 RGND
P
53 RVDD
P
54 PUMPHI I/O
55 PUMPLO I/O
56 PSSYNC I/O
57 PSTEMP I/O
58 PSCURR I/O
59 PWMSYNC I/O
60 PROTECT3 I/O
VOLTAGE
LEVEL
(V)
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
DRIVE
STRENGTH
(mA)
DESCRIPTION
16
General purpose I/O Bidirectional GPIO port. (One of 8 GPIO. Resets to input port. Operation
and assignment is defined by product application's firmware.)
16
General purpose I/O Bidirectional GPIO port. (One of 8 GPIO. Resets to input port. Operation
and assignment is defined by product application's firmware.)
8 - OD
Two-Wire Serial data port 1. Bidirectional signal used by both the master and slave controllers
for data transport.
8 - OD
Two-Wire Serial clock port 1. Bidirectional signal is used by both the master and slave
controllers for clock signaling.
4
PWM protection input with hysteresis. (One of 9 protection inputs. Specific function and
channel assignment is defined by firmware.)
-
S/PDIF Digital audio data input 1
-
S/PDIF Digital audio data input 0
4
S/PDIF Digital audio output. (Audio content and audio processing signal flow is dependent
upon firmware, driving stereo output up to 192kHz.)
-
Factory test use only. Must be tied low.
-
Interrupt request port A, Boot Mode Select. One of 4 IRQ pins. Connects to logic high (3.3V) or
to ground & High/Low logic status establishes boot mode selection upon de-assertion of reset
(nRESET) cycle.
-
Interrupt request port B, Boot Mode Select. One of 4 IRQ pins. Connects to logic high (3.3V) or
to ground & High/Low logic status establishes boot mode selection upon de-assertion of reset
(nRESET) cycle.
-
Interrupt request port C, Boot Mode Select. One of 4 IRQ pins. Connects to logic high (3.3V) or
to ground & High/Low logic status establishes boot mode selection upon de-assertion of reset
(nRESET) cycle.
-
Interrupt request port D, Boot Mode Select. One of 4 IRQ pins. Connects to logic high (3.3V) or
to ground & High/Low logic status establishes boot mode selection upon de-assertion of reset
(nRESET) cycle.
16
Timer I/O port 2. Operation and assignment is controlled by firmware. Leave unconnected
when not in use.
-
Core power, 1.8V
-
Core power, 1.8V
-
Core ground
-
Core ground
-
Digital pad ring ground. Internally connected to PWMGND.
-
Digital pad ring power, 3.3V. This 3.3V supply is used for all the digital I/O pad drivers and
receivers, except for the analog pads. Internally connected to PWMVDD.
16
Assignable I/O. Function and operation defined by firmware.
16
Assignable I/O. Function and operation defined by firmware.
16
Synchronizing output signal to switching power supply. (Operates under specification of
firmware and resets to high impedance inactive state when not used.)
4
Assignable I/O. Function and operation defined by firmware.
4
Assignable I/O. Function and operation defined by firmware.
16
PWM synchronization port. (Function and operation is defined by firmware.)
4
PWM protection input with hysteresis. (One of 9 protection inputs. Specific function and
channel assignment is defined by firmware.)
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FN7838.3
April 28, 2016