ISL6424 Datasheet, PDF (11/12 Pages) Intersil Corporation – Dual Output LNB Supply and Control Voltage Regulator with I2C Interface for Advanced Satellite Set-Top Box Designs

ISL6424
Received Data (I²C bus READ MODE)
The ISL6424 can provide to the master a copy of the system
register information via the I²C bus in read mode. The read
mode is Master activated by sending the chip address with
R/W bit set to 1. At the following Master generated clock bits,
the ISL6424 issues a byte on the SDA data bus line (MSB
transmitted first).
At the ninth clock bit the MCU master can:
• Acknowledge the reception, starting in this way the
transmission of another byte from the ISL6424.
• Not acknowledge, stopping the read mode
communication.
While the whole register is read back by the microprocessor,
the read-only bits OLF1, OLF2, and OTF convey diagnostic
information about the ISL6424.
Power-On I²C Interface Reset
The I²C interface built into the ISL6424 is automatically reset
at power-on. The I²C interface block will receive a Power OK
logic signal from the UVLO circuit. This signal will go HIGH
when chip power is OK. As long as this signal is LOW, the
interface will not respond to any I²C commands and the
system register SR1 and SR2 are initialized to all zeros, thus
keeping the power blocks disabled. Once the Vcc rises
above UVLO, the POWER OK signal given to the I²C
interface block will be HIGH, the I²C interface becomes
operative and the SRs can be configured by the main
microprocessor. About 400mV of hysteresis is provided in
the UVLO threshold to avoid false triggering of the Power-
On reset circuit. (I²C comes up with EN = 0; EN goes HIGH
at the same time as (or later than) all other I²C data for that
PWM becomes valid).
ADDRESS Pin
Connecting this pin to GND the chip I²C interface address is
0001000, but, it is possible to choose between two different
addresses simply by setting this pin at one of the two fixed
voltage levels as shown in Table 8.
TABLE 6. ADDRESS PIN CHARACTERISTICS
V_ADDR
V_ADDR-1
“0001000”
MINIMUM
0V
TYPICAL
-
MAXIMUM
2V
V_ADDR-2
“0001001”
2.7V
-
5V
TABLE 7. READING SYSTEM REGISTERS
DCL ISEL1/2 ENT1/2 LLC1/2 VSEL1/1 EN1/2 OTF2 OLF1/2
FUNCTION
These bits are read as they were after the last write operation.
0
1
T_J ≤ 130°C, normal operation
T_J > 150°C, power blocks disabled
0
I_OUT < I_MAX, normal operation
1
I_OUT > I_MAX, overload protection triggered
I²C Electrical Characteristics
PARAMETER
TABLE 8. I²C SPECIFICATIONS
TEST CONDITION
MINIMUM
TYPICAL
MAXIMUM
Input Logic High, VIH
SDA, SCL
0.7 x V_DD
Input Logic Low, VIL
Input Logic Current, IIL
SCL Clock Frequency
SDA, SCL
SDA, SCL;
0.4V < V_IN < 4.5V
0
0.3 x V_DD
100kHz
10µA
400kHz
11
FN9175.3
September 13, 2005