ISL6422B Datasheet, PDF (11/18 Pages) Intersil Corporation – Dual Output LNB Supply and Control Voltage Regulator with I2C Interface for Advanced Satellite Set-Top Box Designs

ISL6422B
be reached early in the soft-start cycle and a 51ms shutdown
timer will be started again. If the fault is still present at the
end of the 51ms, the OLF bit is again set high and the device
once again enters the 900ms OFF time. This dynamic
operation can greatly reduce the power dissipation in a short
circuit condition, still ensuring excellent power-on start-up in
most conditions.
However, there could be some cases in which a highly
capacitive load on the output may cause a difficult start-up
when the dynamic protection is chosen. This can be solved
by initiating any power start-up in static mode (DCL = HIGH)
and then switching to the dynamic mode (DCL = LOW) after
a chosen amount of time. When in static mode, the OLF1,
OLF2 bit goes HIGH when the current clamp limit is reached
and returns LOW at the end of the initial power on soft-start.
In the static mode the output current through the linears is
limitted to 990mA typ.
When a 19.3V line is connected onto a VOUT1 or VOUT2 that
has been set to 13.3V, the linear will then enter a back current
limited state. When a back current of greater that 140mA typ
is sensed at the lower FET of the linear for a period greater
that 2ms, the output is disabled for a period of 50ms and the
BCF1, BCF2 bit are set. If the 19.3V remains connected, the
output will cycle through the ON = 2ms/OFF = 50ms. The
output will return to the setpoint when the fault is removed.
BCF bit is set high during the 50ms OFF period.
Thermal Protection
This IC is protected against overheating. When the junction
temperature exceeds +150°C (typical), the step-up converter
and the linear regulator are shut off and the OTF bit of the
SR is set HIGH. Normal operation is resumed and the OTF
bit is reset LOW when the junction is cooled down to +130°C
(typical).
If a part is repeatedly driven to the over-temperature
shutdown, the chip is latched off after the fourth occurance
and the I²C bit is latched HIGH and the FLT bar LOW. This
OTF counter and the FLT bar can be reset and the chip
restarted by either a power down/up and reload the I²C or
power can be left on and the reset accomplished by toggling
the I²C bit EN low then back HIGH.
External Output Voltage Selection
The output voltage can be selected by the I²C bus.
Additionally, the package offers two pins (SELVTOP1,
SELVTOP2) for independent 13V thru 19V output voltage
selection.
VSPEN1/2 VTOP1/2
0
x
0
x
0
0
0
1
1
0
1
0
1
1
1
1
TABLE 1.
VOUT1/2
VBOT1/2 SELVTOP1/2
(V)
0
0
13.3
1
0
14.3
x
1
18.3
x
1
19.3
0
x
13.3
1
x
14.3
0
x
18.3
1
x
19.3
I²C Bus Interface for ISL6422B
(Refer to Philips I²C Specification, Rev. 2.1)
Data transmission from main microprocessor to the ISL6422B
(and vice versa) takes place through the two wire I²C bus
interface, consisting of the two lines, SDA and SCL. Both SDA
and SCL are bidirectional lines. They are connected to a
positive supply voltage via a pull-up resistor. (Pull-up resistors
to positive supply voltage must be externally connected). When
the bus is free, both lines are HIGH. The output stages of
ISL6422B will have an open drain/open collector in order to
perform the wired-AND function. Data on the I²C bus can be
transferred up to 100kbps in the standard-mode or up to
400kbps in the fast-mode. The level of logic “0” and logic “1”
depends value of V_DD as per the “Electrical Specifications”
table on page 5. One clock pulse is generated for each data bit
transferred.
Data Validity
The data on the SDA line must be stable during the HIGH
period of the clock. The HIGH or LOW state of the data line
can only change when the clock signal on the SCL line is
LOW. Refer to Figure 4.
SDA
SCL
DATA LINE CHANGE
STABLE OF DATA
DATA VALID ALLOWED
FIGURE 4. DATA VALIDITY
START and STOP Conditions
As shown in Figure 5, START condition is a HIGH to LOW
transition of the SDA line while SCL is HIGH.
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FN6486.1
August 10, 2007