ISL6422B Datasheet, PDF (10/18 Pages) Intersil Corporation – Dual Output LNB Supply and Control Voltage Regulator with I2C Interface for Advanced Satellite Set-Top Box Designs

ISL6422B
Functional Description
The ISL6422B dual output voltage regulator makes an ideal
choice for advanced satellite set-top box and personal video
recorder applications. Both supply and control voltage
outputs for two low-noise blocks (LNBs) are available
simultaneously in any output configuration. The device
utilizes built-in DC/DC step up converters that, from a single
supply source ranging from 8V to 14V, generate the voltages
that enable the linear post-regulators to work with a
minimum of dissipated power. An undervoltage lockout
circuit disables the device when V_CC drops below a fixed
threshold (7.5V typical).
DiSEqC Encoding
The internal oscillator is factory-trimmed to provide a tone of
22kHz in accordance with DiSEqC (EUTELSAT) standards.
No further adjustment is required. The tone oscillator can be
controlled either by the I²C interface (ENT1, ENT2 bit) or by a
dedicated pin (EXTM1, EXTM2) that allows immediate
DiSEqC data encoding separately for each LNB. All the
functions of this IC are controlled via the I²C bus by writing to
the system registers. The same registers can be read back,
and four bits will report the diagnostic status. The internal
oscillator operates the converters at twenty times the 22k tone
frequency. The device offers full I²C compatibility and
supports 2.5V, 3.3V or 5V logic, and up to 400kHz operation.
If the Tone Enable (ENT1, ENT2) bit is set LOW and the
MSEL1, MSEL2 bits set LOW through I²C, then the EXTM1,
EXTM2 terminal activates the internal tone signal,
modulating the DC output with a 680mV_P-P typ symmetrical
tone waveform. The presence of this signal usually provides
the LNB with information about the band to be received.
Burst coding of the tone can be accomplished due to the fast
response of the EXTM1, EXTM2 input and rapid tone
response. This allows implementation of the DiSEqC
(EUTELSAT) protocols.
When the ENT1/2 bit is set HIGH, a continuous 22kHz tone
is generated regardless of the EXTM1, EXTM2 pin logic
status for the corresponding regulator channel (LNB-A or
LNB-B). The ENT1, ENT2 bit must be set LOW when the
EXTM1 and/or EXTM2 pin is used for DiSEqC encoding.
The EXTM1 and EXTM2 pins also accept an externally
modulated tone command when the MSEL1 and MSEL2 I²C
bit is set high.
DiSEqC Decoder
TDIN1, TDIN2 are the inputs to the tone decoders of
Channels 1 and 2 respectively. They accept the tone signal
derived from V_OUT thru the 10nF decoupling capacitor. The
detector threshold can be set to 200mV max in the Receive
mode and to 400mV min in the Transmit mode by means of
the logic presented to the TXT1, TXT2 pin. If tone is
detected, the open drain pins TDOUT1, TDOUT2 are
asserted low. This also enables the tone diagnostics to be
performed, apart from the normal tone detection function.
Linear Regulator
The output linear regulator will sink and source current. This
feature allows full modulation capability into capacitive loads
as high as 0.75µF. In order to minimize the power
dissipation, the output voltage of the internal step-up
converter is adjusted to allow the linear regulator to work at
minimum dropout.
When the device is put in the shutdown mode (EN1,
EN2 = LOW), both PWM power blocks are disabled. (i.e.
when EN1 = 0, PWM1 is disabled, and when EN2 = 0,
PWM2 is disabled).
When the regulator blocks are active (EN1, EN2 = HIGH and
VSPEN1, VSPEN2 = LOW), the output can be controlled via
I²C logic to be 13V/14V or 18V/19V (typical) by means of the
VTOP1, VTOP2 and VBOT1, VBOT2 bits (Voltage Select)
for remote controlling of non-DiSEqC LNBs.
When the regulator blocks are active (EN1, EN2 = HIGH and
VSPEN1, VSPEN2 = HIGH), the VBOT1,VBOT2 and
SELVTOP1, SELVTOP2 pin will control the output between
13V and 14V and the VTOP1, VTOP2 and SELVTOP1,
SELVTOP2 pin will control the output between 18V and 19V.
Output Timing
The output voltage rise and fall times can be set by an the
external capacitor on the TCAP pin. The output rise and fall
times is given by Equation 1:
C
=
3_----2_---7_----._-6_----t
ΔV
(EQ. 1)
Where C is the TCAP value in nF, t is the required slew rate
in ms and ΔV is the differential transition voltage from low
output voltage range to the high output range in Volts.
The recommended value for TCAP is 0.15µF. Too large a
value of TCAP prevents the output from rising to the nominal
value, within the soft-start time when the error amplifier is
released. Too small a value of the TCAP can cause high
peak currents in the boost circuit, for example, a 10V/ms
slew on a 80µF VSW capacitor with an inductor of 15µH can
cause a peak inductor current of approximately 2.3A.
Current Limiting
Dynamic current limiting block has five thresholds that can
be selected by the ISEL1H, ISEL2H , ISEL1L, ISEL2L ,
ISLE1R, ISLE2R bits of the SR. Refer to Table 8 and Table 9
for threshold selection using these bits. The DCL bit has to
be set to low for this mode of operation. In the dynamic
overcurrent mode a fault exceeding the selected overcurrent
threshold for a period greater than 51ms will shutdown the
output for 900ms, during which the I²C bit OLF is set HIGH.
At the end of 900ms, the OLF bit is returned to low state, a
soft-start cycle (~20ms long) is initiated to ramp VSW and
V_OUT back up. If the fault is still present, the overcurrent will
10
FN6486.1
August 10, 2007