ISL5957 Datasheet, PDF (11/13 Pages) Intersil Corporation – 14-Bit, +3.3V, 260+MSPS, High Speed D/A Converter

ISL5957
R_EQ = 0.5 x (R_LOAD//R_DIFF)
AT EACH OUTPUT
PIN 21
PIN 22
ISL5957
IOUTB
R_DIFF
IOUTA
V_OUT = (2 x IOUTA x R_EQ)V
1:1
R_LOAD
R_LOAD REPRESENTS THE
LOAD SEEN BY THE TRANSFORMER
FIGURE 13. OUTPUT LOADING FOR DATASHEET
MEASUREMENTS
R_EQ = 0.5 x (R_LOAD//R_DIFF// R_A), WHERE R_A = R_B
AT EACH OUTPUT
PIN 21
PIN 22
ISL5957
IOUTB
IOUTA
R_A
R_DIFF
R_B
V_OUT = (2 x IOUTA x R_EQ)V
R_LOAD
Propagation Delay
The converter requires two clock rising edges for data to be
represented at the output. Each rising edge of the clock
captures the present data word and outputs the previous
data. The propagation delay is therefore 1/CLK, plus <2ns of
processing. See Figure 15.
Test Service
Intersil offers customer-specific testing of converters with a
service called Testdrive. To submit a request, fill out the
Testdrive form. The form can be found by doing an ‘entire
site search’ at www.intersil.com on the words ‘DAC
Testdrive’. Or, send a request to the technical support center.
R_LOAD REPRESENTS THE
LOAD SEEN BY THE TRANSFORMER
FIGURE 14. ALTERNATIVE OUTPUT LOADING
Timing Diagram
CLK
D13-D0
t_PW1
t_PW2
t_SU
W₀
t_HLD
t_SU
W₁
t_HLD
t_SU
W₂
t_HLD
50%
W₃
I_OUT
t_PD
OUTPUT = W_-1
t_PD
OUTPUT = W₀
OUTPUT = W₁
FIGURE 15. PROPAGATION DELAY, SETUP TIME, HOLD TIME AND MINIMUM PULSE WIDTH DIAGRAM
11
FN6080.1
November 12, 2004