ISL31490E_10 Datasheet, PDF (11/27 Pages) Intersil Corporation – ±60V Fault Protected, 5V, RS-485/RS-422 Transceivers with ±25V Common Mode Range

ISL31490E, ISL31491E, ISL31492E, ISL31493E, ISL31495E, ISL31496E,
Electrical Specifications Test Conditions: V_CC = 4.5V to 5.5V; Unless Otherwise Specified. Typicals are at V_CC = 5V,
T_A = +25°C (Note 10). Boldface limits apply over the operating temperature range,
-40°C to +85°C. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
TEMP MIN
MAX
(°C) (Note 18) TYP (Note 18) UNITS
Receiver Disable from
Output Low
t_LZ
R_L = 1kΩ, C_L = 15pF, SW = V_CC
Full
-
(Figure 6)
-
50
ns
Receiver Disable from
Output High
t_HZ
R_L = 1kΩ, C_L = 15pF, SW = GND
Full
-
(Figure 6)
-
50
ns
Time to Shutdown
t_SHDN (Note 15)
Full
60
160
600
ns
Receiver Enable from
t_ZH(SHDN) R_L = 1kΩ, C_L = 15pF, SW = GND
Full
-
Shutdown to Output High
(Figure 6), (Notes 15, 17)
-
2000
ns
Receiver Enable from
t_ZL(SHDN) R_L = 1kΩ, C_L = 15pF, SW = V_CC
Full
-
Shutdown to Output Low
(Figure 6), (Notes 15, 17)
-
2000
ns
NOTES:
10. All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device
ground unless otherwise specified.
11. Supply current specification is valid for loaded drivers when DE = 0V.
12. Applies to peak current. See “Typical Performance Curves” beginning on page 16 for more information.
13. Keep RE = 0 to prevent the device from entering SHDN.
14. The RE signal high time must be short enough (typically <100ns) to prevent the device from entering SHDN.
15. Transceivers (except on the ISL31491E) are put into shutdown by bringing RE high and DE low. If the inputs are in this state
for less than 60ns, the parts are guaranteed not to enter shutdown. If the inputs are in this state for at least 600ns, the parts
are guaranteed to have entered shutdown. See “Low Power Shutdown Mode” on page 16.
16. Keep RE = VCC, and set the DE signal low time >600ns to ensure that the device enters SHDN.
17. Set the RE signal high time >600ns to ensure that the device enters SHDN.
18. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established
by characterization and are not production tested.
19. Tested according to TIA/EIA-485-A, Section 4.2.6 (±80V for 15μs at a 1% duty cycle).
20. Does not apply to the ISL31491E.
21. See “Caution” statement below the “Recommended Operating Conditions” section on page 6.
Test Circuits and Waveforms
V_CC ^DE
DI
Z
D
Y
V_OD
R_L/2
R_L/2 VOC
V_CC ^DE
DI
Z
D
Y
R_L/2
375Ω
V_OD
V_OC
V_CM
R_L/2 375Ω
FIGURE 1A. V_OD AND V_OC
FIGURE 1B. V_OD AND V_OC WITH COMMON MODE LOAD
FIGURE 1. DC DRIVER TEST CIRCUITS
11
FN7637.0
June 17, 2010