ISL12057 Datasheet, PDF (11/17 Pages) Intersil Corporation – Low Cost and Low Power I2C RTC Real Time Clock/Calendar

ISL12057
TABLE 6. ALARM1 INTERRUPT WITH ENABLE BITS
SELECTION (Continued)
A1DW/DT A1M1 A1M2 A1M3 A1M4 ALARM1 INTERRUPT
X
1
1
0
1
Match Hour
0
1
1
1
0
Match Date
1
1
1
1
0
Match Day
0
0
0
1
1 Match Second and Minute
0
0
1
0
1 Match Second and Hour
0
0
0
0
0 Match Second, Minute
and Hour
.
.
.
.
.
.
.
.
.
.
.
.
0
1
0
0
0 Match Minute Hour and
Date
0
0
0
0
0 Match Second, Minute
Hour and Date
.
.
.
.
.
.
.
.
.
.
.
.
1
1
0
0
0 Match Minute, Hour, and
Day
1
0
0
0
0 Match Second, Minute,
Hour, and Day
Note: X is don’t care, it can be set to 0 or 1.
Following is example of Alarm1 Interrupt.
Example – A single alarm will occur on Monday at 11:30am
(Monday is when DW = 2).
A. Set Alarm1 registers as follows:
ALARM1
BIT
REGISTER 7 6 5 4 3 2 1 0 HEX DESCRIPTION
A1SC 1 0 0 0 0 0 0 0 80h Seconds disabled
A1MN 0 0 1 1 0 0 0 0 30h Minutes set to 30,
enabled
A1HR
0 1 0 1 0 0 0 1 51h Hours set to 11am,
enabled
A1DW/DT 0 1 0 0 0 0 1 0 42h Day set to 1,
enabled
After these registers are set, an alarm will be generated when
the RTC advances to exactly 11:30am on January 1 (after
seconds changes from 59 to 00) by setting the A1F bit in the
status register to “1”.
Alarm2 Registers
Addresses [Address 12h to 14h]
The Alarm2 register bytes are set up identical to the RTC
register bytes except that the MSB of each byte functions as
an enable bit (enable = “0”). These enable bits specify which
alarm registers (minutes, hour, and date/day) are used to
make the comparison. When all the enable bits are set to “1”,
the Alarm2 will trigger once per minute. Note that there are
no alarm bytes for second, month and year.
The Alarm2 function works as a comparison between the
Alarm2 registers and the RTC registers. As the RTC
advances, the Alarm2 will be triggered once a match occurs
between the Alarm2 registers and the RTC registers. Any
one Alarm2 register, multiple registers, or all registers can be
enabled for a match.
To clear an Alarm2, the A2F status bit must be set to “0” with
a write.
TABLE 7. ALARM2 INTERRUPT WITH ENABLE BITS
SELECTION
A2DW/DT A2M2 A2M3 A2M4 ALARM2 INTERRUPT
X
1
1
1 Every Minute (Second=00)
X
0
1
1
Match Minute
X
1
0
1
Match Hour
0
1
1
0
Match Date
1
1
1
0
Match Day
X
0
0
1
Match Minute and Hour
0
1
0
0
Match Hour and Date
0
0
1
0
Match Minute and Date
0
0
0
0 Match Minute, Hour, and Date
1
0
1
0
Match Minute and Day
1
1
0
0
Match Hour and Day
1
0
0
0 Match Minute, Hour, and Day
Note: X is don’t care, it can be set to 0 or 1.
Following is example of Alarm2 Interrupt.
Example – A single alarm will occur on every 1st day of the
month at 20:00 military time.
A. Set Alarm registers as follows:
ALARM2
BIT
REGISTER 7 6 5 4 3 2 1 0 HEX DESCRIPTION
A2MN 1 0 0 0 0 0 0 0 80h Minutes disabled
A2HR 0 0 1 0 0 0 0 0 20h Hours set to 20,
enabled
A2DW/DT 0 0 0 0 0 0 0 1 01h Date set to 1st,
enabled
After these registers are set, an alarm will be generated when
the RTC advances to exactly 20:00 on Monday (after minutes
changes from 59 to 00) by setting the A2F bit in the status
register to “1”.
11
FN6755.0
June 15, 2009