ICM7217_01 Datasheet, PDF (11/20 Pages) Intersil Corporation – 4-Digit LED Display, Programmable Up/Down Counter

ICM7217
V_DD = 5V
35
LCD DISPLAY
37 - 40
2 - 26
28 SEGMENTS
AND BACKPLANE
34
D4
33
D3
32
D2
ICM7211
31
D1
30
DB3
29
DB2
28
DB1
27
DB0
V_DD = 5V
4 _8s
5 _4s
6 _2s
7 _1s
24
V_DD
23
DC
20
8
COUNT
9
STORE
10
UP/DN
14
RESET
D1 ²⁸
D2 ²⁷
ICM7217
IJI ^{D3 26}
D4 25
24
1
8
C
24
1
8
C
24
1
8
C
24
1
8
C
10kΩ - 20kΩ
FIGURE 14. LCD DISPLAY INTERFACE (WITH THUMBWHEEL SWITCHES)
The lCM7217A and the ICM7217C are used to drive com-
mon cathode displays, and the BCD inputs are low true.
BCD outputs are high true.
Notes on Thumbwheel Switches and Multiplexing
As it was mentioned, the ICM7217 is basically designed to
be used with thumbwheel switches for loading the data to
the device. See Figure 14 and Figure 17.
The thumbwheel switches used with these circuits (both
common anode and common cathode) are TRUE BCD
coded; i.e. all switches open corresponds to 0000. Since the
thumbwheel switches are connected in parallel, diodes must
be provided to prevent crosstalk between digits. In order to
maintain reasonable noise margins, these diodes should be
specified with low forward voltage drops (IN914). Similarly, if
the BCD outputs are to be used, resistors should be inserted
in the Digit lines to avoid loading problems.
Output and Input Restrictions
LOAD COUNTER and LOAD REGISTER operations take
1.6ms typical (5ms maximum) after LC or LR are released.
During this load period the EQUAL and ZERO outputs are
not valid (see Figure 3). Since the Counter and register are
compared by XOR gates, loading the counter or register can
cause erroneous glitches on the EQUAL and ZERO outputs
when codes cross.
LOAD COUNTER or LOAD REGISTER, and RESET input
can not be activated at the same time or within a short period
of each other. Operation of each input must be delayed
1.6ms typical (5ms for guaranteed proper operation) relating
to the preceding one.
Counter and register can be loaded together with the same
value if LC and LR inputs become activated exactly at the
same time.
Notice the setup and hold time of UP/DOWN input when it is
changing during counting operation. Violation of UP/ DOWN
hold time will result in incrementing or decrementing the
counter by 1000, 100 or 10 where the preceding digit is
transitioning from 5 to 6 or 6 to 5.
The RESET input may be susceptible to noise if its input rise
time is greater than about 500µs This will present no prob-
lems when this input is driven by active devices (i.e., TTL or
CMOS logic) but in hardwired systems adding virtually any
capacitance to the RESET input can cause trouble. A simple
circuit which provides a reliable power-up reset and a fast
rise time on the RESET input is shown on Figure 15.
11