ISL6742 Datasheet, PDF (10/18 Pages) Intersil Corporation – Advanced Double-Ended PWM Controller

ISL6742
The maximum duty cycle, D, and percent deadtime, DT, can
be calculated from:
D
=
---^t--^C-----
t_SW
(EQ. 4)
DT = 1 – D
(EQ. 5)
Soft-Start Operation
The ISL6742 features a soft-start using an external capacitor in
conjunction with an internal current source. Soft-start reduces
component stresses and surge currents during start-up.
Upon start-up, the soft-start circuitry limits the error voltage
input (VERR) to a value equal to the soft-start voltage. The
output pulse width increases as the soft-start capacitor voltage
increases. This has the effect of increasing the duty cycle from
zero to the regulation pulse width during the soft-start period.
When the soft-start voltage exceeds the error voltage, soft-
start is completed. Soft-start occurs during start-up and after
recovery from a fault condition. The soft-start charging period
may be calculated using Equation 6:
t = 64.3 ⋅ C ms
(EQ. 6)
where t is the charging period in ms and C is the value of the
soft-start capacitor in µF. The soft-start duration experienced
by the power supply will be less than or equal to this value,
depending on when the feedback loop takes control.
The soft-start voltage is clamped to 4.50V with an overall
tolerance of 2%. It is suitable for use as a “soft-started”
reference provided the current draw is kept well below the
70µA charging current.
The outputs may be inhibited by using the SS pin as a
disable input. Pulling SS below 0.25V forces all outputs low.
An open collector/drain configuration may be used to couple
the disable signal to the SS pin.
Gate Drive
The ISL6742 outputs are capable of sourcing and sinking
10mA (at rated VOH, VOL) and are intended to be used in
conjunction with integrated FET drivers or discrete bipolar
totem pole drivers. The typical ON-resistance of the outputs
is 50Ω.
Overcurrent Operation
Two overcurrent protection mechanisms are available to the
power supply designer. The first method is cycle-by-cycle
peak overcurrent protection, which provides fast response.
The second method is a slower, averaging method, which
produces constant or “brick-wall” current limit behavior. If
voltage-mode control is used, the average overcurrent
protection also maintains flux balance in the transformer by
maintaining duty cycle symmetry between half-cycles.
The current sense signal applied to the CS pin connects to the
peak current comparator and a sample and hold averaging
circuit. After a 70ns leading edge blanking (LEB) delay, the
current sense signal is actively sampled during the on-time,
the average current for the cycle is determined, and the result
is amplified by 4x and output on the IOUT pin. If an RC filter is
placed on the CS input, its time constant should not exceed
~50ns or significant error may be introduced on IOUT.
CHANNEL 1 (YELLOW): OUTA
CHANNEL 3 (BLUE): CS
CHANNEL 2 (RED): OUTB
CHANNEL 4 (GREEN): IOUT
FIGURE 5. CS INPUT vs IOUT
Figure 5 shows the relationship between the CS signal and
IOUT under steady state conditions. IOUT is 4x the average
of CS. Figure 6 shows the dynamic behavior of the current
averaging circuitry when CS is modulated by an external
sine wave. Notice IOUT is updated by the sample and hold
circuitry at the termination of the active output pulse.
CHANNEL 1 (YELLOW): OUTA
CHANNEL 3 (BLUE): CS
CHANNEL 2 (RED): OUTB
CHANNEL 4 (GREEN): IOUT
FIGURE 6. DYNAMIC BEHAVIOR OF CS vs IOUT
10
FN9183.2
October 31, 2008