ISL55033 Datasheet, PDF (10/12 Pages) Intersil Corporation – 400MHz Slew Rate Enhanced Rail-to-Rail Output Gain Block

EN
IN+_1
IN+_2
IN+_3
R_IN 1
R_IN 2
R_IN 3
GND_IN(1, 2, 3)
ISL55033
DECOUPLING
CAPACITORS
V+
V+_OUT
GND_OUT(1,2,3)
R_OUT 1
R_OUT 2
R_OUT 3
OUT_1
OUT_2
OUT_3
FIGURE 32. BASIC APPLICATION CIRCUIT
Application Information
General
The ISL55033 single supply, fixed gain, triple amplifier is
intended for use in a variety of video and other high speed
applications. The device features a ground-sensing PNP
input stage and a bipolar rail-to-rail output stage. The three
amplifiers have an internally fixed gain of 2, and share a
single enable pin as shown in Figure 32.
Ground Connections
For the best isolation performance and crosstalk rejection,
all GND pins must connect directly to the GND plane. In
addition, the electrically conductive thermal pad must also
connect directly to ground.
Power Considerations
Separate V+ power supply and GND pins for the input and
output stages are provided to maximize PSRR. Providing
separate power pins provides a way to prevent high speed
transient currents in the output stage from bleeding into the
sensitive amplifier input and gain stages. To maximize
crosstalk isolation, each power supply pin should have its
own de-coupling capacitors connected as close to the pin as
possible as shown in Figure 30 (0.1µF in parallel with 1nF
recommended).
The ESD protection circuits use internal diodes from all pins to
the V₊ and ground pins. In addition, a dV/dt-triggered clamp is
connected between the V₊ and V_- pins, as shown in the
Equivalent Circuits 1 through 4 in Figure 32. The dV/dt
triggered clamp imposes a maximum supply turn-on slew rate
of 1V/µs. Damaging currents can flow for power supply
rates-of-rise in excess of 1V/µs, such as during hot plugging.
Under these conditions, additional methods should be
employed to ensure the maximum rates-of-rise is not
exceeded.
Single Supply Input/Output Considerations
For best performance, the input signal voltage range should
be maintained between 0.1V to 2.1V. These input limits
correspond to an output voltage range of 0.2V to 4.2V and
define the limits of linear operation. Figure 4 shows the
frequency response versus the input DC voltage level.
Figures 16 and 17 show the differential gain-phase
performance over the input range of 0V to 2.4V operating
into a 150Ω load. The 0.1V to 2.1V input levels corresponds
to a 0.2V to 4.2V output levels, which define the minimum
and maximum range of output linear operation.
Composite video with sync requires care to ensure that the
negative sync tip voltage (typically -300mV) is properly
level-shifted up into the ISL55033 input linear operating
region of +0.1V to 2.1V. The high input impedance enables
AC coupling using low values of coupling capacitance with
relatively high input voltage divider resistances.
EN and Power-Down States
The EN pin is active low. An internal pull-down resistor
ensures the device will be active with no connection to the
EN pin. The power-down state is established within
approximately 25ns, if a logic high (>2V) is placed on the EN
pin. In the power-down state, supply current is reduced
significantly by shutting the three amplifiers off. The output
presents a relatively high impedance (~2kΩ) to the output
pin. Multiplexing several outputs together is possible using
the enable/disable function as long as the application can
tolerate the limited power-down output impedance.
10
FN6346.0
September 11, 2008