ISL54405_14 Datasheet, PDF (10/20 Pages) Intersil Corporation – CD/MP3 Quality Stereo 2:1 Multiplexer with Click and Pop Elimination

ISL54405
1. All active shunt switches turn off quickly.
2. The resistance of the switches selected by the SEL pin will
gradually decrease in resistance. They will decrease from
their high OFF-resistance to their ON-resistance of 1.9.
This gradual decrease in resistance will allow for the
voltage at the load to increase gradually. The voltage ramp
rate at the load is determined by the value of the capacitor
connected at the CAP_SS pin, see Figures 28 and 29 on
page 16.
Table 1 indicates how the signal ramp rate at the load changes
as you change the CAP_SS capacitor value. It also shows how
the mute turn-on time is affected.
TABLE 1. SIGNAL RAMP-RATE LOAD CHANGE WITH CAP SS
CAPACITOR VALUE
RAMP RATE
TURN-ON TIME
No Capacitor
6250V/s
65µs
0.05µF
10.3V/s
30ms
0.1µF
4.6V/s
58ms
ON TO MUTE
When the MUTE pin is driven HIGH, the switches will turn off
quickly (50ns) and the active shunt switches will turn on
quickly. Note: There is no gradual ramping of the switch
resistance in this direction.
OFF-ISOLATION IN THE MUTE STATE
When in the mute state, the level of OFF-Isolation across the
audio band is dependent on the signal amplitude, external
loading, and location of the activated C/P (click/pop) shunt
circuitry. During muting, the logic of the ISL54405 can be
configured to activate the C/P shunt circuitry on the load side
of the switch or on the source side of the switch, or deactivated
on both sides of the switch.
With a 0.707V_RMS signal driving a 32 headphone load, the
location of the C/P shunt circuitry has little effect on the
off-isolation performance (>120dB of off-isolation in all
configurations), see Figure 12 on page 13.
With a 2V_RMS signal driving a 20k amplifier load, the best
OFF-Isolation is achieved by placing the C/P shunt circuitry on
the load side of the switch (>120dB across the audio band).
The OFF-Isolation decreases when placing the C/P shunt
circuitry on the source side of the switch (>85dB across the
audio band), see Figure 11 on page 13.
Note: For AC coupled applications when powering up or down
of the audio drivers the C/P shunts should be activated on the
source side of the switch. See “Click and Pop Operation” on
page 11.
When using the switch for muting of the audio signal the C/P
shunt circuitry should be deactivated on the source side of the
switch and directed to the load side of the switch for best
possible OFF-Isolation.
Logic Control
The ISL54405 has four logic control pins; the AC/DC, DIR_SEL,
MUTE, and SEL. The MUTE and SEL control pins determine the
state of the switches. The AC/DC and DIR_SEL control pins
determine the location of the C/P (click/pop) shunt circuitry
and if it will be active or not. See “Truth Table” on page 3.
The ISL54405 logic is 1.8V CMOS compatible (Low 0.5V and
High 1.4V) over a supply range of 3.0V to 3.6V at the VDD pin
or 4.5V to 5.5V at the 5V_Supply pin. This allows control via
1.8V or 3V µ-controller.
SEL, MUTE CONTROL PINS
The state of the SPDT switches of the ISL54405 device is
determined by the voltage at the MUTE pin and the SEL pin.
The SEL control pin is only active when MUTE is logic “0”. The
MUTE has an internal pull-up resistor to the internal 3.3V
supply rail and can be driven HIGH or tri-stated (floated) by the
µ-processor.
These pins are 1.8V logic compatible. When powering the part
by the VDD pin the logic voltage can be as high as the V_DD
voltage which is typically 3.3V. When powering the part by the
5V_Supply pin the logic voltage can be as high as the
5V_Supply voltage which is typically 5V.
Logic Levels:
MUTE = Logic “0” (Low) when 0.5V
MUTE = Logic “1” (High) when 1.4V or floating
SEL = Logic “0” (Low) when 0.5V
SEL = Logic “1” (High) when 1.4V
AC/DC AND DIR_SEL CONTROL PINS
The ISL54405 contains C/P (click/pop) shunt circuitry on its
COM pins (L, R) and on its signal pins (L1, R1, L2, R2). The
activation of this circuitry and whether it is located on the COM
or signal side of the switch is determined by the logic levels
applied at the AC/DC and DIR_SEL pins. The DIR_SEL control
pin is only active when AC/DC is logic “1”. Note: Any activated
C/P shunt circuitry is ON when in the mute state (MUTE = Logic
“1”) and OFF in the audio state (MUTE = Logic “0”).
When AC/DC is logic “0”, all of the C/P shunt circuitry on both
sides of the switch is deactivated and not operable.
When AC/DC is logic “1” then the DIR_SEL logic level
determines whether the shunt circuitry will be activated on the
COM side of the switch or on the signal side of the switch.
When DIR_SEL = Logic “1” the C/P shunts on the COM side
(L,R) are activated and inoperable on the signal side (L1, R1,
L2, R2) of the switch. When DIR_SEL = Logic “0” the C/P
shunts are activated on the signal side (L1, R1, L2, R2) and
inoperable on the COM side (L, R).
Logic Levels:
AC/DC, DIR_SEL = Logic “0” (Low) when 0.5V
AC/DC, DIR_SEL = Logic “1” (High) when 1.4V or Floating.
The AC/DC and DIR_SEL have internal pull-up resistors to the
internal 3.3V supply rail and can be driven HIGH or tri-stated
(floated by the µ-processor). They should be driven to ground
for a logic “0” (Low). Note: For 5V applications, the AC/DC and
DIR_SEL pins should never be driven to the external 5V rail.
They need to be driven with 1.8V logic or 3V logic circuit.
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FN6699.2
May 6, 2014