ISL5100A Datasheet, PDF (10/13 Pages) Intersil Corporation – Quad 18V Pin Electronics Driver/Window Comparator

ISL55100A
The maximum power dissipation actually produced by an IC
is the total quiescent supply current times the total power
supply voltage, plus the power in the IC due to the loads.
Power also depends on number of channels changing state,
frequency of operation. The extent of continuous active
pattern generation/reception will greatly effect dissipation
requirements.
The power dissipation curves (Figure 16), provide a way to
see if the device will overheat. The maximum safe power
temperature vs operating frequency can be found graphically
in Figure 17. This graph is based on the package type Theta
JA ratings and actual current/wattage requirements of the
ISL55100 when driving a 1K load with a 6V High Level and a
0V Low Rail. The temperatures are indicated as calculated
junction temperature over the ambient temperature of the
user’s system. Plots indicate temperature change as
operating frequency increases. (The graph assumes
continuous operation.) The user should evaluate various
heat sink/cooling options in order to control the ambient
temperature part of the equation. This is especially true if the
users applications require continuos, high speed operation.
The reader is cautioned against assuming the same
level of thermal performance in actual applications. A
careful inspection of conditions in your application
should be conducted. Great care must be taken to
ensure Die Temperature does not exceed Absolute
Maximum Thermal Limits.
Important Note: The ISL55100 package metal plane is
used for heat sinking of the device. It is electrically
connected to the negative supply potential (V_EE). If V_EE
is tied to ground, the thermal pad can be connected to
ground. Otherwise, the thermal pad (V_EE) must be
isolated from other power planes.
Power Supply Sequencing
The ISL55100 references every supply with respect to VEE.
Therefore apply VEE, then VCC followed by the VH,VL
busses, then the COMP High and Comp Low followed by the
CVA & CVB Supplies. Digital Inputs should be set with a
differential bias as soon as possible. In cases where V_EXT is
being utilized (V_EXT = V_EE+ 5.5v), it should be powered up
immediately after V_CC. Basically, no pin should be biased
above V_CC or below V_EE.
Data Rates
Please note that the Frequency - MHz in Figures 16 and 17
contain two transitions within each period. A digital
application that requires a new test pattern every 50ns would
be running at a 20MHz Data Rate. Figure 18 reveals 100ns
period, in 10MHz frequency parlance, results in two 50ns
digital patterns.
Typical Performance Curves Device installed on Intersil ISL55100 Evaluation Board.
VV_CECE
12.0
- 3.0
VH
VL
2.0
0.0
LOWSWING OFF
0
LOWSWING ON
0
10ns/DIV
FIGURE 6. LOWSWING EFFECTS ON DRIVER SHAPE AND
T_PD (100pF-1K LOAD)
0
DATA IN
1K/100pF
680pF
2200pF
1000pF
0
VV_CECE
12.0
- 3.0
VH
VL
6.0
0.0
10ns/DIV
FIGURE 7. DRIVER WAVEFORMS UNDER VARIOUS LOADS
10
FN7486.0
October 31, 2005