ISL43231 Datasheet, PDF (10/15 Pages) Intersil Corporation – Low-Voltage, Single and Dual Supply, Triple SPDT Analog Switch

ISL43231
Test Circuits and Waveforms (Continued)
3V
LOGIC
INPUT
0V
t_r < 20ns
t_f < 20ns
SWITCH
OUTPUT
V_OUT
0V
t_BBM
80%
C
V+
LOGIC
INPUT
V+
C
V-
C
EN, LE
NC_X, NO_X
ADD_X
COM_X
GND EN
V_OUT
R_L
300Ω
C_L
35pF
Repeat test for other switches. C_L includes fixture and stray
capacitance.
FIGURE 3A. t_BBM MEASUREMENT POINTS
FIGURE 3B. t_BBM TEST CIRCUIT
FIGURE 3. BREAK-BEFORE-MAKE TIME
t_MPW
t_r < 20ns
t_f < 20ns
LOGIC ^3V
INPUT
LE
0V
50%
t_H
LOGIC ^3V
INPUT
ADD_{X 0V}
50%
t_S
50%
50%
t_H
50%
t_ON, t_OFF
VNC_X
SWITCH
OUTPUT
0V
V_OUT
90%
Logic input waveform is inverted for switches that have the opposite
logic sense.
V+
V-
C
C
C
LOGIC
INPUT
LOGIC
INPUT
EN
ADD_X
NC_X
V+
NO_X
V_OUT
LE _{GND EN} COM_X
R_L
300Ω
C_L
35pF
Repeat test for other switches. C_L includes fixture and stray
capacitance.
V_OUT
=
V(NO _{or NC)}
------------^R-----^L-------------
R_L + R_(ON)
FIGURE 4A. LATCH t_S, t_H, t_MPW MEASUREMENT POINTS
FIGURE 4B. LATCH t_S, t_H, t_MPW TEST CIRCUIT
FIGURE 4. LATCH SETUP AND HOLD TIMES
V+
C
V-
C
SIGNAL
GENERATOR
EN, LE
NO or NC
ANALYZER
R_L
ADD_X
0V or V+
COM _GND
0V or V+
EN
FIGURE 5. OFF ISOLATION TEST CIRCUIT
10
V+
C
V-
C
R_ON = V₁/1mA
V_NX
EN, LE
NO or NC
1mA
V₁
0V or V+
ADD_X
COM
GND EN
FIGURE 6. R_ON TEST CIRCUIT