ICL7135 Datasheet, PDF (10/15 Pages) Intersil Corporation – 4 1/2 Digit, BCD Output, A/D Converter

ICL7135
POL
A
A
V⁺
+5
DM
3K
8880
G
G RB0 PROG
RBI ^BI D
A
0V
+5V ^{HI VOLTAGE BUFFER D1 505} 47K
5K
0.02µF
2.5K
GATES
ARE
7409
POL D5
0.02µF
D1
B8
ICL7135
B1
V+
+5
DGND
0V
FIGURE 8. ICL7135 PLASMA DISPLAY CIRCUIT
+5V
4¹/₂ DIGIT LCD DISPLAY
BP
23 POL ¹/2 CD4030
20 D1
CD4081
1/4 CD4030
19 D2
5 BP
31 D1
32 D2
18 D3
17 D4
33 D3
34 D4
16 B8
15 B4
14 B2
13 B1
CD4071
30 B3
29 B2
28 B1
27 B0
12 D5
26 STROBE
27 OR
CD4011 ICM7211A
ICL7135
+5V
1_{/4 CD4030}
FIGURE 9. LCD DISPLAY WITH DIGIT BLANKING ON
OVERRANGE
A problem sometimes encountered with both LED and plasma-
type display driving is that of clock source supply line variations.
Since the supply is shared with the display, any variation in
voltage due to the display reading may cause clock supply
voltage modulation. When in overrange the display alternates
between a blank display and the 0000 overrange indication.
This shift occurs during the reference integrate phase of
conversion causing a low display reading just after overrange
recovery. Both of the above circuits have considerable current
flowing in the digital supply from drivers, etc. A clock source
using an LM311 voltage comparator with positive feedback
(Figure 11) could minimize any clock frequency shift problem.
The ICL7135 is designed to work from ±5V supplies.
However, if a negative supply is not available, it can be
generated with an ICL7660 and two capacitors (Figure 12).
Interfacing with UARTs and
Microprocessors
Figure 13 shows a very simple interface between a free-running
ICL7135 and a UART. The five STROBE pulses start the
transmission of the five data words. The digit 5 word is
0000XXXX, digit 4 is 1000XXXX, digit 3 is 0100XXXX, etc. Also
the polarity is transmitted indirectly by using it to drive the Even
Parity Enable Pin (EPE). If EPE of the receiver is held low, a
parity flag at the receiver can be decoded as a positive signal,
no flag as negative. A complex arrangement is shown in Figure
14. Here the UART can instruct the A/D to begin a
measurement sequence by a word on RRl. The BUSY signal
resets the Data Ready Reset (DRR). Again STROBE starts the
transmit sequence. A quad 2 input multiplexer is used to
superimpose polarity, over-range, and under-range onto the D5
word since in this instance it is known that B2 = B4 = B8 = 0.
For correct operation it is important that the UART clock be fast
enough that each word is transmitted before the next STROBE
pulse arrives. Parity is locked into the UART at load time but
does not change in this connection during an output stream.
Circuits to interface the ICL7135 directly with three popular
microprocessors are shown in Figure 15 and Figure 16. The
8080/8048 and the MC6800 groups with 8-bit buses need to
have polarity, over-range and under-range multiplexed onto
the Digit 5 Sword - as in the UART circuit. In each case the
microprocessor can instruct the A/D when to begin a
measurement and when to hold this measurement.
Application Notes
NOTE #
DESCRIPTION
AN016 “Selecting A/D Converters”
AN017 “The Integrating A/D Converter”
AN018 “Do’s and Don’ts of Applying A/D
Converters”
AN023 “Low Cost Digital Panel Meter Designs”
AN028 “Building an Auto-Ranging DMM Using
the 8052A/7103A A/D Converter Pair”
AN030 “The ICL7104 - A Binary Output A/D
Converter for Microprocessors”
AN032 “Understanding the Auto-Zero and
Common Mode Performance of the
ICL7136/7/9 Family”
AnswerFAX
DOC. #
9016
9017
9018
9023
9028
9030
9032
10
FN3093.3